LS1043A device Tree Modifications

[Naveenkumar_Muthusamy]

Hi,

we are using LS1043ARDB Board for our development. we are trying to changes the few Parameters for Testing. we would like to know few details about the device tree and how that can be validated.

1) Regarding the GPIO Pin configuration - how to configure a specific GPIO as Input and Output in Device tree

2) GPIO configurations for a Specific Interface -  For Ex: if i am using RGMII1 and RGMII2, - my understanding is somewhere in dts, it has to mentioned that a specific set of GPIO are configured for RGMII1 and RGMII2. This information, i am unable to find it in device tree. i have checked fsl-ls1043rdb.dts and other files related to it.

3) In our custom board we will be using Marvell 88e1512 PHY for RGMII1, so mapping this PHY to MDIO is necessary, but it is still unclear about the base addresss of the mdio in the reference manual.

4) Do we have any tool which can be used for generating dtsi for GPIO configuration or any tool just to verify GPIO configurations for the interfaces are valid.

5) we will be using DDR4 in our system, as per reference manual, DDR1 controller supports upto max 2GB? and DDR2 supports upto 30GB?

6) if we try to boot from EMMC and remove all the NAND and NOR Flash from the design, what are all the necessary precautions that should be considered? for ex , do we need to flash the initial boot files in some memory? 

@yipingwang LS1043A 

[yipingwang]

reg in dts refers to the address of phy, mdio will detect the device while scanning this address. eg:
                     qsgmii_phy1: ethernet-phy@4 {
                             reg = <0x4>;
                     }; 

3) In our custom board we will be using Marvell 88e1512 PHY for RGMII1, so mapping this PHY to MDIO is necessary.

 6) NO need to flash the initial boot files.

[yipingwang]

5) There is only one DDR controler, no DDR2 controler on LS1043A.
there are four physical banks (chip selects), each bank independently addressable
- 64-Mbit to 16-Gbit devices depending on internal device configuration
- Supports x8/x16 data ports
When LS1043A uses 4 chip selects and each with a 16Gb density DDR4 x16 RAM, the maximum supported capacity is 8GB.
PCB routing complexity: The presence of 4 chip selects will increase the difficulty of the layout.

[yipingwang]

1) Regarding the GPIO Pin configuration - how to configure a specific GPIO as Input and Output in Device tree
- Customer can refer to <LSDKUG_Rev21.08> Chapter 7.2.23, to configure a specific GPIO, they must check the pin in RCW, if it's used as other function, they need to disable it, and change it to GPIO function. After flashing new RCW, they can configure the direction in uboot and linux to test.
If they want to configure it in dts, they can use gpio-hog to configure. Refer to <Documentation/devicetree/bindings/gpio/gpio.txt>
Customer can also configure the direction of a specific GPIO in driver (drivers/gpio/gpio-mpc8xxx.c) using gc->direction_input and gc->direction_output.
2)
Does customer mean the configuration for pinmux of GPIO? It's configured in RCW.
4)
AFAIK, we don't have such tool.

I will ask others to answer the question 3/5/6 later.

[Naveenkumar_Muthusamy]

Hi @yipingwang ,

any updates?