LS1043A: SERDES-PLL reset causes PHY link fail

[MaxLiou]

Dear NXP,

By reference to below solution:

/Layerscape/How-to-configure-Ethernet-SGMII-MAC9-on-LS1043A/m-p/626613 

Our Marvell switch can work normally with intentionally perform  SERDES-PLL reset.

But once we perform  SERDES-PLL reset, the PHY becomes malfunction.

(PHY works perfect before perform SERDES-PLL reset)

HW connect as below:

PHY-->   DATA: Lane 0 of SERDES, Control: EMI1_MDIO

switch--> DATA: Lane 1 of SERDES, Control: EMI1_MDIO (same MDIO bus)

My test step as below:

1. (PHY) ping 192.168.1.23 --> works

2. (switch)ping 192.168.1.113 -->fail

3. (perform PLL reset) --> do like reference describe.

4. (switch)ping 192.168.1.113 -->works

5. (PHY) ping 192.168.1.23 -->fail , which is our problem here.

Please help us on this.

Thanks a lot.

[yipingwang]

Please provide the following details:
1) SerDes Dump before and after PLL reset.
2) Which SerDes protocol is selected? (If you have RCW+PBI, then it will help.)
3) Can you try PHY reset first before SerDes PLL reset?

[MaxLiou]

Dear Yiping,

I tried the reset you mention on your last comment and it didn't work.

I have tried PHY reset before SerDes PLL reset , and PHY reset after SerDes PLL reset,

both are PHY link fail.  

Our SerDes protocol is 0x2255, also upload rcw as attachment.

I will upload the rest data later.

Best Regards,

Max

[yipingwang · Accepted solution]

PBI commands have already been included in rcw_1000_sdboot.

[MaxLiou]

Dear Yiping,

SerDes Dump as my attachment.

Regarding the PBI, can you kindly tell me where the file's location?

I can't find this PBI file.

Best Regards,

Max

[yipingwang]

Please do the following procedure to reset the SerDes PLL:

Customer's SerDes Protocol: 0x2255 --> sg.m9 (2.5G), sg.m2 (2.5G), PCIe 2 (x1), PCIe 3 (x1)

Please ask the customer to do the following procedure:

1) Read the values of Protocol Configuration Register 8 (PCCR8) at offset 0x220.

2) Read General Control Register 0: LNAGCR0 (at 0x800 offset) and LNBGCR0 (at 0x840 offset)

        If LNmGCR0[RPLL_LES]=1, then do,

1. a) Write 0xC000_0000 the register at offset 0x1800 for Lane A and at offset 0x1810 for Lane B. For example, "devmem 0x1ea1800 32 0x000000C0" and "devmem 0x1ea1810 32 0x000000C0".
2. b) Write PCCR8[SGMIIn_CFG]=000
3. c) Set PLLnRSTCTL[RST_REQ]=1 to reset SerDes PLL1

3) After the SerDes PLL reset is complete (PLLnRSTCTL[RST_DONE]=1), then do,

1. a) Write PCCR8 with the values read in step 1
2. b) For each register written with 0xC000_0000 in steps 2, write 0x8000_0000.

Note: It is recommended to quiesce and disable the Ethernet MACs during this reset. See DPAA RM 6.5.5 Graceful stop for details.