LS1043A: Marvell 88e6341 on SerDes lane B and EMI1/EC1

[BeatS]

Hello

We have a custom designed board based on the LS1043A, which has a Marvell 88e6341 switch connected to SerDes lane B and EC1/EMI1. The SerDes configuration is 0x2255.

Unfortunately I don't have an idea how to modify the device tree to get this running. I try to use the device tree files of the ls1043ardb reference board of Layerscape SDK2004 as a basis.

I would be very grateful for any advice.

Best regards,
Beat Straehl

[yipingwang]

For device tree binding definitions, please refer to DSA standard, refer to the kernel document

Documentation/devicetree/bindings/net/dsa/dsa.txt

ethernet-switch@0,5 {
       reg = <0x000500 0 0 0 0>;
       /* IEP INT_B */
       interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
       ports {
             #address-cells = <1>;
             #size-cells = <0>;
             /* external ports */
            port@0 {
                      reg = <0>;
                      label = "swp0";
           };
           port@1 {
                  reg = <1>;
                  label = "swp1";
           };
          port@2 {
                   reg = <2>;
                   label = "swp2";
           };
         port@3 {
                 reg = <3>;
                 label = "swp3";
          };
         /* internal to-cpu ports */
         port@4 {
                reg = <4>;
                ethernet = <&enetc_port2>;
                phy-mode = "gmii";
                fixed-link {
                      speed = <2500>;
                       full-duplex;
                };
         };
         port@5 {
                 reg = <5>;
                 phy-mode = "gmii";
                 status = "disabled";
                 fixed-link {
                        speed = <1000>;
                         full-duplex;
                  };
               };
          };
};

[BeatS]

Thank you for your reply. I use the device tree sources for the ls1043a-rdb reference board as a basis and changed only the &fman0 section of file fsl-ls1043a-rdb.dts as follows:

&fman0 {
	ethernet@e2000 {
		phy-connection-type = "sgmii";
		fixed-link = <0 1 1000 0 0>;
	};

	switch_eth: ethernet@e4000 {
		phy-handle = <&cpuport>;
		phy-connection-type = "rgmii-id";
		fixed-link = <0 1 1000 0 0>;
	};


	mdio@fc000 {
		switch0: switch0@0 {
		    compatible = "marvell,mv88e6341";
		    #address-cells = <1>;
		    #size-cells = <0>;
		    reg = <0x0>;
		    reset-gpios = <&gpio3 12 0>;
		    ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
			    reg = <0>;
			    label = "lan0";
			};
			port@1 {
			    reg = <1>;
			    label = "lan1";
			};
			port@2 {
			    reg = <2>;
			    label = "lan2";
			};
			port@3 {
			    reg = <3>;
			    label = "lan3";
			};
                        cpuport: port@4 {
                            reg = <4>;
                            label = "cpu";
                            ethernet = <&switch_eth>;
                            fixed-link {
                                speed = <1000>;
                                full-duplex;
                            };
                        };
		    };
		};
	};

	mdio@fd000 {
		aqr105_phy: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c45";
			interrupts = <0 132 4>;
			reg = <0x1>;
		};
	};
};

The probing of the Marvell chip fails late with error -517. The problem seems to be that somehow the reference from the CPU port to the ethernet interface is not working. Function dsa_port_parse_of in dsa2.c fails because of_find_net_device_by_node(ethernet); returns NULL.

static int dsa_port_parse_of(struct dsa_port *dp, struct device_node *dn)
{
	struct device_node *ethernet = of_parse_phandle(dn, "ethernet", 0);
	const char *name = of_get_property(dn, "label", NULL);
	bool link = of_property_read_bool(dn, "link");

	dp->dn = dn;

	if (ethernet) {
		struct net_device *master;

		master = of_find_net_device_by_node(ethernet);
		if (!master) {
			printk(KERN_ERR "*************** dsa_port_parse_of3 %s\n", ethernet->full_name);
			return -EPROBE_DEFER;
		}
		return dsa_port_parse_cpu(dp, master);
	}

	if (link)
		return dsa_port_parse_dsa(dp);

	return dsa_port_parse_user(dp, name);
}

However, the full name of the ethernet name ethernet->full_name is correctly read from the device tree and is "ethernet@e4000".

Any ideas?

[yipingwang]

On LS1043A –

ethernet@e0000 {

        phy-connection-type = "sgmii-2500";

        fixed-link {

                speed = <1000>;

                full-duplex;

        };

    };

On Marvell dts

port@0 {

            phy-mode = "2500base-x";

            fixed-link {

                speed = <2500>;

                full-duplex;

            };

    };

Also please make sure your kernel has following patch - https://source.codeaurora.org/external/qoriq/qoriq-components/linux/commit/?h=git.kernel.org/master&...

If the sgmii-2500 patch is not there in the kernel codebase, you can even say sgmii there in phy connection type and try.

[BeatS]

I can use ethernet@e2000 with is configured to be on SerDes lane b which is connected to the Marvel 88e6341 and MAC  ethernet@4000 is connected to the RGMII interface of the switch chip. So I adapted your suggestion to ethernet@e2000. But then I don't understand why I should configure the MAC as a fixed link with one 1Gb/s, while the phy-connection-type is smii-2500 and the switch port is fixedly configured to run a 2.5Gb/s. And then the smgii-cpu-port of the 88e6341 is port 5. Also I have to declare port 5 to be the CPU port with the "ethernet" clause. So I modified your suggestion to:

&fman0 {
	switcheth1: ethernet@e2000 {
	        phy-connection-type = "sgmii-2500";
	        fixed-link {
	                speed = <2500>;
	                full-duplex;
	        };
	};

	mdio@fc000 {
		switch0: switch0@0 {
			compatible = "marvell,mv88e6341";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;

			interrupts-extended = <&extirq 11 IRQ_TYPE_LEVEL_LOW>;
			reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port5: port@5 {
					reg = <5>;
					label = "cpu";
					phy-mode = "2500base-x";
					ethernet = <&fman0_rx_0x09>; // doesn't work with switcheth1. I have to reference a parent of it.
					local-mac-address = [42 00 00 00 00 80];
					fixed-link {
						speed = <2500>;
						full-duplex;
					};
				};

But it doesn't work. I always get "mv88e6085 1afc000:00: Timeout while waiting for switch".

[BeatS · Accepted solution]

Hi Yiping

Thank you for your hints, which put me in the right direction. I also understand now, that it's important to specify a fixed speed of 1000Mb/s for the MAC. It's because the phy software emulation doesn't understand 2500Mb/s currently. So this is the device tree, which makes the MAC2 over the SerDes lane B between the SoC and the mv88e6341 working.

&fman0 {
	ethernet@e2000 {
	        phy-connection-type = "sgmii-2500";
	        fixed-link {
	                speed = <1000>;
	                full-duplex;
	        };
	};

	mdio@fc000 {
		switch0: switch0@0 {
			compatible = "marvell,mv88e6341";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;

			interrupts-extended = <&extirq 11 IRQ_TYPE_LEVEL_LOW>;
			reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port5: port@5 {
					reg = <5>;
					label = "cpu";
					phy-mode = "2500base-x";
					ethernet = <&fman0_rx_0x09>;
					local-mac-address = [42 00 00 00 00 80];
					fixed-link {
						speed = <2500>;
						full-duplex;
					};
				};

				port@1 {
					reg = <1>;
					label = "swp0";
					phy-handle = <&switch0phy1>;
					local-mac-address = [42 00 00 00 00 81];
				};

				port@2 {
					reg = <2>;
					label = "swp1";
					phy-handle = <&switch0phy2>;
					local-mac-address = [42 00 00 00 00 82];
				};

				port@3 {
					reg = <3>;
					label = "swp2";
					phy-handle = <&switch0phy3>;
					local-mac-address = [42 00 00 00 00 83];
				};

				port@4 {
					reg = <4>;
					label = "swp3";
					phy-handle = <&switch0phy4>;
					local-mac-address = [42 00 00 00 00 84];
				};
			};

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				switch0phy1: switch0phy0@11 {
					reg = <0x11>;
				};
				switch0phy2: switch0phy1@12 {
					reg = <0x12>;
				};
				switch0phy3: switch0phy2@13 {
					reg = <0x13>;
				};
				switch0phy4: switch0phy3@14 {
					reg = <0x14>;
				};
			};
		};
	};
};

As you can see above the Marvell 88e6341's SGMII cpu port is port 5. And for some reasons I still don't fully understand, I had to disable the C_MODE configuration for port 5, which would otherwise run into a timeout.

index 8ef81f2dc..db669b77c 100644
--- a/packages/linux/linux/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/packages/linux/linux/drivers/net/dsa/mv88e6xxx/chip.c
@@ -624,12 +624,14 @@ int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link,
}

-       if (chip->info->ops->port_set_cmode) {
-               err = chip->info->ops->port_set_cmode(chip, port, mode);
-               if (err && err != -EOPNOTSUPP)
-                       goto restore_link;
-       }
+  if (port!=5) {
+    if (chip->info->ops->port_set_cmode) {
+      err = chip->info->ops->port_set_cmode(chip, port, mode);
+      if (err && err != -EOPNOTSUPP)
+        goto restore_link;
+    }
+  }

err = 0;

But now the switch is working properly and can be configured from userspace using tools such as ip or bridge. Thanks a lot.