LS1043A DDR3L Address Routing

[serkanOz]

Hi,

We are currently designing LS1043A board with DDR3L 32+4bit interface. I have a question at that point about address matching for fly by topology. AN3940 states as follows;
"• Tune signals to +/-10 mils of the clock at each device"

What does it mean? There are two options about it.

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Board Design Address Routing;

LS1043A ----- L1 ----- |DDR3L1| ----- L2 ----- |DDR3L2| ----- L3 ----- |DDR3L3| ---- Termination

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1. Option

L1 = +/-10mil match between address-clock
L2 = +/-10mil match between address-clock
L3 = +/-10mil match between address-clock

DDR3L1 will have 10mils tolerance in worst case.
DDR3L2 will have 20mils tolerance in worst case.
DDR3L3 will have 30mils tolerance in worst case.

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2. Option
L1             = +/-10mil match between address-clock
L1+L2       = +/-10mil match between address-clock
L1+L2+L3 = +/-10mil match between address-clock

DDR3L1 will have 10mils tolerance in worst case.
DDR3L2 will have 10mils tolerance in worst case.
DDR3L3 will have 10mils tolerance in worst case.

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Which options is mentioned by AN3940? If the second option is mentioned, it is a bit strict for maximum 1600Mbit/s (for LS1043A) interface.

Have a nice day

[Bulat · Accepted solution]

You are right, the app note says "Tune signals to +/-10 mils of the clock at each device". This statement corresponds to option 2 in your description, regardless of device position in the fly-by chain, all address/command/control signals at the device should be +/-10 mils of the clock. This is specified for 2133MT/s speed, can be slightly relaxed for 1600MT/s, but we can not provide numeric values for this relaxing.

Regards,

Bulat

[serkanOz]

Thanks for your explanation.