LS1028A could not get PHY in U-Boot

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LS1028A could not get PHY in U-Boot

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ainolike
Contributor III

Hi,

I'm developing my project with LS1028A. On my board the management interface (MDC/MDIO) of AR8031 connects to EMDIO. PHY address is 2. I read the PHY register using the following commands in U-Boot:

=>mdio read 2 0

Reading from bus emdio-3

PHY at address 2:

TT0 - 0x0

According U-Boot code, I know the character ‘T’ means MDIO busy. The EMDIO_CFG register definition gives us the description of all the bits. But how is BSY field set to 1? Does it set by hardware? and in what circumstances will it be set to 1?

 

Besides, I have another test that disconnects the MDIO/MDC between LS1028 and AR8031.  BSY field is still 1.

 

 

 

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ainolike
Contributor III

I make a test that is removing lsf0204 from our board. And the MDIO is no longer busy. 

Two PHY chips are connected to lsf0204. When disconnect one, theother can be read normally.

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ufedor
NXP TechSupport
NXP TechSupport

Please provide raw memory dump of the EMDIO registers and DEVDISR2.

 

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ainolike
Contributor III

This problem is probably a hardware problem, because our hardware has some changes. The same U-Boot image can find PHY on the development board.

I want to know what the MDIO busy implementation mechanism is, which is not described in detail in LS1028ARM.pdf.

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ufedor
NXP TechSupport
NXP TechSupport

> our hardware has some changes.

Which exactly changes?

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ainolike
Contributor III

I make a test that is removing lsf0204 from our board. And the MDIO is no longer busy. 

Two PHY chips are connected to lsf0204. When disconnect one, theother can be read normally.

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xinliwang
Contributor III

Hi, @ainolike 

I met the same problem on my project. The reference board has two phy chips(RGMII QSGMII interface) connected to the lsf0204 which work very well. And we add another phy (RGMII interaface) and cause the MDIO BUSY occasionally. Can you tell me how to fix it on your project in the end?

Thank you 

xinli

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ainolike
Contributor III

There is a lsf0204 between LS1028A and PHY MDC/MDIO interface. PHY chip is disconnected from lsf0204, the BSY bit of register is still 1.

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ainolike
Contributor III

I don't know much about hardware. Our hardware engineers say that it's a matter of electrical level.

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ainolike
Contributor III

=> md 0x1f8101c00

1f8101c00: 80839549 00008000 00000000 00000003

1f8101c10: 00030001 00000000 00000000 00000000

1f8101c20: 00000000 00000000 00000000 00000000

1f8101c30: 00000000 00000000 00000000 00000000

 

=> md 0x1e00074

01e00074: 00000000 00000000 00000000 00000000

01e00084: 00000000 00000000 00000000 00000000

01e00094: 00000000 00000000 00000000 00000000

01e000a4: 870b0110 00000040 00000000 00000000

 

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