LS1021a DDR register descriptions and ECC error injection

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LS1021a DDR register descriptions and ECC error injection

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bgilsrud
Contributor I

Hi,

I'm looking at the DDR register descriptions in the LS1021a reference manual (LS1021ARM Rev. 0, 11/2015) and the documentation doesn't appear to be accurate when I compare the register description to the actual contents read from a TWR-LS1021A board. Here are some examples:

DDR_IP_REV1

root@ls1021atwr:~# devmem 0x1080bf8  
0x01050200
The register description indicates that IP_ID should be 0x0002, but it's 0x0200. Maybe the documentation isn't up to date for IP 0x200?

DDR_SDRAM_CFG

root@ls1021atwr:~# devmem 0x1080110
0x08000CC7
The SDRAM_TYPE field is 0b110 which is "Reserved" according the the register description.

There are more inconsistencies, but this is a good representation of the problems I'm having. I would like to be able to use the DDR injection mechanism for testing but it doesn't seem to do anything. My guess is that the documentation is incorrect but maybe I'm doing something wrong...any ideas?

Thanks,

Ben

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bgilsrud
Contributor I

I just noticed that the DDR section of the CCSR is marked as big-endian. I had suspected that my problems were caused by endianess (the IP_ID of 0x0002 compared to 0x0200 was a big hint) but I rejected that since some values still don't make sense after doing the byte swaps. An example of this is the DDR_SDRAM_CFG field that I already mentioned. The MEM_EN field (bit 0) must be a 1 since the memory controller is obviously enabled. No other arrangement of the word would satisfy this.

Thanks,

Ben

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ufedor
NXP TechSupport
NXP TechSupport

Your assumption about the endianness is correct.

The 32-bit register values you've captured have to be converted as follows:

0x01050200 -> 0x00020501

0x08000CC7 -> 0xC70C0008

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