Points to check:
1) SYSCLK has correct frequency, is present at the processor's pin(s) and is properly selected.
cfg_eng_use0 selects between SYSCLK (single ended) and DIFF_SYSCLK/DIFF_SYSCLK_B (differential) clock inputs - refer to the AN4878 - LS1021A Design Checklist, Table 8. LS1021A reset configuration signals, IFC_WE0_B.
2) PORESET_B is asserted for at least 1ms (after all power supplies are stable) - refer to the QorIQ LS1021A Data Sheet, Table 24. RESET initialization timing specifications.
3) TRST_B is pulsed low during POR - refer to the Design Checklist, Table 61. JTAG system-level checklist, Boundary-scan testing.
4) Use a digital scope to check POR levels of all configuration signals described in the Design Checklist, Table 8. LS1021A reset configuration signals to ensure, in particular, that RCW source is selected properly.
5) Use a digital scope to ensure that all signals with Note 5 in ht eQorIQ LS1021A Data Sheet, Table 1. Pinout list by bus are not pulled low during POR.