LS1021A Tower Board TBI internal phy link failure

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LS1021A Tower Board TBI internal phy link failure

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romitchatterjee
Contributor V

I am writing an Ethernet device driver for the LS1021A Tower board, running a custom OS. eTSEC3 is working fine in RGMII mode. eTSEC1 and eTSEC3 are detected as SGMII and status register of external phy confirm that link is up. However, TBI status register shows that the interface is down. Is there any procedure to check the status of SerDes module? Do I need to set anything in SerDes module or somewhere else?

I am also not getting any RX/TX interrupt in eTSEC1 and eTSEC2.

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romitchatterjee
Contributor V

It is working. Have to set CPLD register offset 0x0D to 0x04.

u-boot does it .. so if you are using u-boot then it should work. Check SerDes protocol in RCW.

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bpe
NXP Employee
NXP Employee

Suggestions:

1. Follow the steps specified in LS1021ARM, Section 20.10.1.4

2. Make sure you are accessing all registers at their correct addresses.

3. Study the following documents for better understanding:
   (a) NXP Application Note AN3869;
   (b) CISCO Systems document ENG-46158 (SGMII Specification),
       Page 7;

4. Refer to u-Boot SGMII link bringup code, file tsec.c function
   tsec_configure_serdes().


Have a great day,
Platon

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romitchatterjee
Contributor V

Thank you for your suggestions.

I tried all those steps that you mentioned except 3.(b). I will check that.

I suspect that my register access mechanism may have some problems. Before reading/writing TBI registers, I am writing the Phy address (0x1f) in eTSEC1 TBIPA register. According to the specification (LS1021ARM), if I access TBI registers for eTSEC2 then I must write Phy address in eTSEC2 TBIPA register. But  in that case, I have always got 0xffff when I read any TBI register.  If I write Phy address in eTSEC1 TBIPA, then only I get reset values of TBI registers.

Do you have any idea what am I doing wrong?

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swanandpurankar
Contributor III

Hi,

This thread was very helpful to me. Glad that you posted steps you followed/problems you faced and their solutions!

I have a question. When you say,

Before reading/writing TBI registers, I am writing the Phy address (0x1f) in eTSEC1 TBIPA register. According to the specification (LS1021ARM), if I access TBI registers for eTSEC2 then I must write Phy address in eTSEC2 TBIPA register

I don't understand what is eTSEC2's PHY address? My understading was When I load some address in eTSEC1 TBIPA, I should load same value in all TBIPA registers.

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romitchatterjee
Contributor V

I am being able to run eTSEC2 port as SGMII and ping is working. So current condition is eTSEC2 and eTSEC3 are working but eTSEC1 is not working.

Please note that I have already changed the protocol of serdes to 0x30. So eTSEC1 is detected as SGMII interfaces but TBI SR shows that link is down and also I am not getting any RX/TX interrupt. Output of my RCW is as follows.

00000000: 0608000a 00000000 00000000 00000000
00000010: 30000000 00007900 e0025a00 21046000
00000020: 00000000 00000000 00000000 20000000
00000030: 00080000 481b7340 00000000 00000000

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romitchatterjee
Contributor V

It is working. Have to set CPLD register offset 0x0D to 0x04.

u-boot does it .. so if you are using u-boot then it should work. Check SerDes protocol in RCW.