LS1021A RCW fields clarification (IFC, SYSCLK,QSPI, etc.)

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LS1021A RCW fields clarification (IFC, SYSCLK,QSPI, etc.)

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Contributor V

Hi,

So my boot source is eMMC which is hard wired strapped.

Now back to RCW settings datasheet says

PBI_SRC 1110 is the IFC mode

Then IFC_MODE says cfg_rcw_src[0:8] 0_0100_0000  is SD/MMC (eSDHC) are multiplexed on
{IFC_AD[8:15], IFC_CLE} --------------------------------------> this is super confused 

and this is also noted as 1 .Not valid as an RCW[IFC_MODE] encoding.

From my code warrior when I set PBI_SRC as 1110

pastedImage_4.png

the IFC_MODE does not have 0_0100_0000 this option at all.

(1)Can someone explains?

(2) Since I am using eMMC do I need to care about QSPI clock frequency ?

pastedImage_1.png

(3) I also have this error: RCW and PBI data must be loaded from the same source.

pastedImage_1.png

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NXP TechSupport
NXP TechSupport

this is super confused 

What exactly is confusing?

> the IFC_MODE does not have 0_0100_0000 this option at all

This is because IFC is not multiplexed with the SDHC interface.

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Contributor V

The confusion is  IFC_MODE says cfg_rcw_src[0:8] 0_0100_0000  is SD/MMC (eSDHC) are multiplexed on
{IFC_AD[8:15], IFC_CLE}  then what is IFC)MODE (these 9 bits for ) but I think you already answered they are not multiplexed on these registers

so if I need to set boot source as eMMC in the RCW what should I do ? Just strapped up the signals of cfg_rcw_src ?

pastedImage_1.png

Also can you look at (3) as well?

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NXP TechSupport
NXP TechSupport

The shown strapping is not correct.

The "1" in the cfg_rcw_src[0:8] 0_0100_0000 corresponds to the IFC_AD10.

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Contributor V

(1) I think that is a mistake but before that I want to double confirm with you

pastedImage_4.png

Are you saying leftmost bit is bit 0 and rightmost bit is bit 8??

(2) what should I put in

pastedImage_1.png

PBI_SRC  0110?

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NXP TechSupport
NXP TechSupport

1) Yes.

2) When PBI_SRC is configured for IFC, this field selects the IFC mode for pre-boot initialization.

The field setting is don't care if PBI_SRC is not equal 1110 (IFC).

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Contributor V

pastedImage_1.png

Does this match the boot requirement from eMMC?

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NXP TechSupport
NXP TechSupport

This is OK.

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Contributor V

Hi ufedor,

I am facing JTAG detection issue so I found this thread LS1021a TAP Error 

In the end that guy says pastedImage_2.png

This is my eMMC strapping

pastedImage_6.png

(1) In order to make the hard-coded RCW works do I have to hard strapping these pins cfg_rcw_src[0:8] (like pulling down or up by resistors) then after I done I strap back to eMMC

(2) If not how this works by changing cfg_rcw_src[0:8] into 0x9A

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NXP TechSupport
NXP TechSupport

1) Your understanding is correct.

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Contributor V

is hard-coded RCW is the only option for me to bring a board up with empty eMMC and has no RCW in flash?

As this guy says

pastedImage_1.png

forcing a valid RCW through JTAG (is this can be done without cfg_rcw_src pins strapping) by just using CW?

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NXP TechSupport
NXP TechSupport

It is possible to override RCW - refer to the CodeWarrior for ARMv7 Targeting Manual, 8.2 Using a JTAG configuration file to override RCW.

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Contributor V

can you take a look at this config file

pastedImage_1.png

is the highlighted place should be (0 0x9b) or (1 0x9b)

this is the config file I am using for the hard-coded option

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NXP TechSupport
NXP TechSupport

It should be (0 0x9b) - reference:

"\CW_ARMv7_v2019.01\CW_ARMv7\ARMv7\ARM_Support\Configuration_Files\jtag_chains\LS102xATWR_RCW_1000-300-1600.txt"

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