I need to create a PCIe extension card which must support multiple MSIs, not MSI-X which is not possible on the card. Reading the LS1021A Reference Manual (Rev. 0, 11/2015) 10.2.47 SCFG_PEXMSIIR is the register which must be programmed as the Message Address Register to PCIe EP. The current driver pcie-designware + pci-layerscape does this.
So when a MSI occures the MSI Message Data contains the MSI number, e.g. 0h, 1h, 2h and so on, which is written to SCFG_PEXMSIIR in little-endian. Now reading the register definition IBS, containing the lowest byte of MSI Message Data, ignores the lowest 3 bits at all. MSI requires that MSi numbers are consequtive for one EP. How is this supposed to work if the lowest bits are ignored at all?
