LS1021A GPIO usage peculiarity

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LS1021A GPIO usage peculiarity

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fdm
Contributor IV

Hi,

There is some information concerning GPIO pins usage in LS1021A:

Based on feedback from SW/design team If we want use all the GPIO3, we should set all the GPIO3 pin by RCW.

Include: EC1,EC2,EC3 and MDC_MDIO. You don't have option to only select subset of the GPIO3 pins. This is applicable to all GPIO ports.

416-418 EC1 = 001 GPIO3[2:14]

419-421 EC2 =001 GPIO3[15:27]

422-424 EC3 =001 GPIO3[28:31]

425-426 MDC_MDIO =01 GPIO3[0:1]

Unfortunately this information not explained in the RM.

I am not sure if I understand this right. Is it mandatory to set all 4 groups of GPIO3 related RCW bits to the "GPIO" state in order to use only two GPIO3 pins (GPIO3_13 and GPIO3_14 in that use case), thus making e.g. eTSEC3 RGMII interface unusable?

In contrast with the foregoing, one of our custom LS1021A based boards successfully uses SDHC interface and GPIO2_24 pin as GPIO output simultaneously despite of the fact that GPIO2[4:9] pins are shared with SDHC.

As far as I know, this fact is not documented so far.

Is there any additional background info on this issue?

BR,
   Denis

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fdm
Contributor IV

Having created a Service Request on this issue, I've obtained two responses:

  1. Mentioned threads can be interpreted in a way that it is not possible to use partial GPIO3 ports, all should be used.
    This is wrong conclusion, and statement from the community "You don't have an option to only select subset of the GPIO3 pins." is also wrong.
  2. Information provided in the thread #365969 is out of date.

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fdm
Contributor IV

Having created a Service Request on this issue, I've obtained two responses:

  1. Mentioned threads can be interpreted in a way that it is not possible to use partial GPIO3 ports, all should be used.
    This is wrong conclusion, and statement from the community "You don't have an option to only select subset of the GPIO3 pins." is also wrong.
  2. Information provided in the thread #365969 is out of date.
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r8070z
NXP Employee
NXP Employee


Have a great day,

It is supposed that each GPIO RCW field controls only own group of GPIOn pins. You could see that for the GPIO2 pins. But according to https://community.nxp.com/thread/365969#comment-570991 there is hardware issue for  the GPIO3 pins. As result all these 4 fields should be set for GPIO3 even for one group using.

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