We are developping control board using NSX LS1021A,
we have met d-cache problem.
We are now writing diag software as u-boot loadable programs,
since u-boot loadble modules can access fully hardware features.
Since we could not archive expected performance, we checked
program activity, and found I-cache is working, but D-cache is not.
We also checked using TWR-LS1021A-PB of freescale. The result is same.
Attached screen images are Lauterbach T32ARM's debug windows.
According to u-boot source code, u-boot enables I-cache and D-cache
using MMU. U-boot setups translation tables with long-descriptor
translation table format, normal memory, write-back write-allocate.
In image of TWRLS1021A-1.jpg, upper left window shows TLB,
upper right shows I-cache, middle right shows D-cache,
bottom center shows page table.
In image of TMWLS1021A-2.jpg,upper three windows show several registers,
bottom windows shows level-1 translation table. The table contains
4 long-descriptor entries.
1st: 0xbfff1003 00000000 # 1GB device memory and pcie ?
2nd: 0x40000411 00000000 # 1GB device memory
3rd: 0x8000041d 00000000 # 1GB normal memory, write-back, write-allocate
4th: 0xC000041d 00000000 # 1GB normal memory, write-back, write-allocate
In TLB window, 5th entry (idx=05) may be TLB of 3rd descriptor, because
of phisical address range mathing.
The logical adderss of the entry seems to be strange.
It should be C:80000000-BFFFFFFF, instead of 00000000--3FFFFFFF.
After boot linux, above problem disappear, and TLB and caches seem to be good.
When linux comes, I imagine some fixes may be done by OS code.
Is there any fixes or ERRATA, for enabling D-cache in u-boot
or for u-boot loadable modules
Taizo Kojima, Mitsubishi Electric Corp. Itami Works. Japan.
D-cache could not be enabled because snoop could not used in u-boot, there is cache coherence problem after enabling d-cache.
Thank you for replying to my question.
I think 'snoop could not used in u-boot' means that, device drivers such as ethernet
in u-boot expects uncacheable area for use. Is it right?
I can avoid this problem. During executing our programs, d-cache is on,
and before exiting our programs, flushing cache and disable d-cache.
One of our member founds in Cortex-A7 MPCore Technical Reference Manual,
‘ACTLR.SMP must be set to 1 for enabling d-cache’.
We try setting ACTLR.SMP to 1, and confirm d-cache is on.
We are now testing, and hope the result will begood.
Hello Taizo Kojima,
Yes, enabling d-cache the Ethernet driver cannot work normally in u-boot. You could set SMP bit to enable d-cache, and use the software method to flushing d-cache, if you want to use Ethernet in u-boot.