LS1021 Boundary Scan Length Failure

[anthonykriege]

I am having issues accessing/enabling the boundary scan register (SAMPLE, PRELOAD, EXTEST, etc) on our LS1021.  The device responds correctly to bypass and device id commands, but not to tests that utilize the boundary scan register. 

I have confirmed the compliance pins are being set correctly.  Is there any order/sequencing that needs to be maintained with these pins?  I have confirmed TRST_F is being toggled prior to the test beginning and is staying high afterwards.

I have multiple cards/test fixtures that exhibit this failure.  I haven't been able to replicate 100%, but occasionally the boundary scan register will function correctly.  This gives me confidence that the physical connections are solid, but I have some underlying sequencing issue and/or a floating signal somewhere.

[ErfanehV]

I have the exact same issue as Anthony, and have already tried the ~2000 JTAG Clock cycles, but have not got any result yet. Is any special pattern required on TMS or any  other JTAG signal, that I'm ignoring?

[alexander_yakov]

We have solved this already via direct online technical support case.

The USB PHY requires ~2000 JTAG clock cycles to come out of reset before to it can become a part of boundary scan register.

Have a great day,
Alexander
TIC

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