LS1020E - IFC Addressing Mode 1

[dusanferbas]

I started a new thread as requested by Alexander at Query on cfg_rcw_src[6:7] in RCW Source Encoding.

Question is how to connect 16 bit NOR flash memory to the LS1020 in ADM mode 1?

Maybe I am a big endian guy for a long time, but anyhow.

In the reference manual (LS1021ARM.pdf), chapter 23.4.1.2.2 Mode 1 pin muxing, figure 23-16, there is a description, how internal address is shifted to be divided into AD and ADDR buses. Also for 16 bit access only even addresses make sense, thus the lsb is shifted out. As far as clear, but why do we need bit reverse? The figure 23-16 shows bit to bit wiring, AD0 to AD0 on memory or probably a discrete solution with a latch. On the contrary, figure 23-16 shows address bit 30 going to signal AD0. Can someone explain this?

"Right shift the swapped address by ADM_SHFT programmed to align msb to index 31 (in same line as in left shift mode)". Why the msb is marked as 4? Does it mean the address is hold in address register in big endian order?

Now, where the realpoint is: if we come to booting, change to rcw_src is required. We can select ADM shift of 4, which is probably for 8 bit memories. Will this rcw_src setup work with 16 bit memories? I think yes, but as they did not, I would like to eliminate this problem.

[alexander_yakov]

Your questions are not numbered, so I will try to answer in given order:

1. Example 16bit NOR flash connection is shown at Figure 23-64.

2. You not need reverse, the fact that reverse is available does not mean you have to use it. Reverse may be useful in some cases, but it is absolytely up to designer to use reverese or not. For example, if you have 16bit memory device with small number of address lines, reverse is useful so you can multiplex least significant addresses with data to save external address lines for other purposes. Figure 23-26 shows the same - in reversed least significant address becomes AD0. That is - normally AD0 is most significant address and data bit, but because of address reverse it starts reflicting least significant address line A30.

3. Regarding rightshift of swapped address. The device does not have so much unmuxed address lines. After reverse, you will have A30 to A15 reflected on AD bus, so remaining unmuxed address lines should be used for other address lines starting from A14, so there will be no gap in address layout. Rightshifting allows A14 to be shifted to first addres line which is available externally (A16 in this case).

4. If you wish to boot from this device, than you have to configure this shifting by selecting one of shifting options available in RCW. Please look Table 4-9, there are only several options - right/left shift and shift by 10, 7 or 4

Have a great day,
Alexander

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[dusanferbas]

ad 1. Yes, but the Figure 23-64 connects the NOR flash in shift mode 0 (pin muxing mode 0).
I would like to connect PC28F00BM29EWHA (256 MB) in pin muxing mode 1, i.e. latch on IFC_AD0:15, from latch to memory A0-A15. IFC_A16:26 to memory A16:26. This works for reading / writing after booting from SD card.
I think this is case, shown in the Figure 23-13.

But we are unable to boot from IFC NOR flash, even if we select cfg_rcw_src[5]=1, to shift address right.
I assume the "address shift right" in Table 4-9 has same meaning as CSORn[ADM_SHFT_MODE] = 1 (in chapter 23.4.1.2).

ad 3. I am unable to catch the point. The Figure 23-13 has a same wiring for Figure 23-12. Example 2 (address only swapped, not shifted) as the Figure 23-17 has for Figure 23-16. Example 4 (address swapped and right shifted).

Note:The ADM_SHFT=5 cannot be select for RCW source. I think 5 is for 128 MB flash and 4 is for 256 MB flash?

[dusanferbas]

The reason was in timing - a flash has to be out of reset when CPU is getting data from it. However this is obvious, we used HRESET- for flash, but this signal is still asserted during the time, CPU is loading its RCW. After redesigning our reset logic, booting from NOR flash started to work and we are still running without a CPLD. 1 AND gate and 2 level shifters are sufficient for our application.