I post this message in order to share our experience about issues with LS1020A QSPI Boot (also valid for LS1021).
The sample RCW files provided in LSDK all contain a command which change the divider for QSPI clock speed:
write 0x57015c, 0x00000803
Where does this value come from?
Explanation:
- It is a write to SCFG_QSPI_CFG
- As the endianess has not been setup yet, the value to be written is bit-flipped from what you can find in the reference manual.
- The value given in the RCW examples (0x00000803), when bit-flipped, is 0xC0100000:
- The "1" is a default value for bit 11
- The is a strange value since the high-order bit must be 0 as described in the reference manual.
- If we ignore the high-order bit (which is what the CPU seems to do), the divider value is 100 which correspond to PLL/20. I confirmed this divider with an oscilloscope.
- If we replace this value with 0x00000802 (the same but without the strange bit), the result is the same.
- I tested other values and all of them worked as expected
I hope this message will help others to setup the speed of their QSPI bus.
