LS1012A, muxing cfg_sysclk_sel and QSPI_CS

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LS1012A, muxing cfg_sysclk_sel and QSPI_CS

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Contributor II

Hi,

I'd like to know for how long after PORESET de-assertion should the QSPI chip select of the NOR flash be separated from the CPU and its cfg_sysclk_sel.
CPU is using an external osc., so the sysclk_sel needs to be pulled down during reset, but NOR can't have its CS pulled down during power-up (it needs a high-to-low transition before accepting any commands). Therefore, according to datasheet (Table 12), the two need to be separated for at least 16ns after PORESET_B is de-asserted.

If my understanding is correct, why does LS1012ARDB (rev. D) then use a ~33us delay (RC) on DRV_PORCFG_B that enables the switch separating CPU's CS from the flashes'? I figured a delay too long might be an issue, when CPU tries to read RCW from flash and pulls CS down, but gets nothing from the flash because its CS is still disconnected and pulled up... Correct?

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NXP TechSupport
NXP TechSupport

The muxing in question works properly with LS1012A silicon rev.1.0 which starts rcw fetch after about 400us after PORESET deassertion.

For the LS1012A rev.2.0 this timing is 5.1us, so the muxing delay has to be reduced.

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1 Reply
17 Views
NXP TechSupport
NXP TechSupport

The muxing in question works properly with LS1012A silicon rev.1.0 which starts rcw fetch after about 400us after PORESET deassertion.

For the LS1012A rev.2.0 this timing is 5.1us, so the muxing delay has to be reduced.

View solution in original post