LS1012A connected to switch without PHY

[igor_franco]

Hello,

I am using a custom board based on the LS1012A processor. This board uses the SerDes protocol 0x3508, which means that my MAC1 is SGMII (1G) and the MAC2 is RGMII. Both SerDes MACs are directly connected to a KSZ9477 Switch (MAC-MAC). I am doing the support in the U-Boot to allow the firmware update via TFTP. But both interfaces can not communicate with a simple ping. 

I configured the custom board based on the LS1012A-FRWY board. I have compared it with the LS1012ARDB because it uses the same schema for the MAC ports. However, I did not see any significant change that could help me solve the problem. I will divide this question for each Ethernet mode.

SGMII:

The pfe_eth driver could connect to the PFE_MDIO and configure it with a fixed link of 1Gbps/Full Duplex. However, when I read the status register of the MDIO, it shows that the link is down (see image below). Considering that the LS1012A uses PFE firmware, is there something I need to do to allow a MAC-MAC link? Or could the problem be in the hardware? 

igor_franco_0-1626433779069.png

RGMII:

The RGMII (MAC2) does not even configure the MDIO (see the image below). Does the internal MDIO work with the RGMII? How can I configure the RGMII to work directly with the switch?

igor_franco_1-1626436153520.png

I am using the LSDK-20.04-update_290520 for the U-Boot. The RCW configures the SerDes to use the internal 125MHz clock. And we are using the TFA configuration settings.

Thank you in advance,

Igor

[yipingwang]

You need to modify u-boot source code board/freescale/ls1012afrdm/eth.c according to your custom board.

You could replace board/freescale/ls1012afrdm/eth.c with board/freescale/ls1012ardb/eth.c, then delete the following section in this file.

case 0x3508:
// if (!priv->gemac_port) {
/* MAC1 */
// pfe_set_phy_address_mode(priv->gemac_port,
// CONFIG_PFE_EMAC1_PHY_ADDR,
// PHY_INTERFACE_MODE_SGMII);
// } else {
/* MAC2 */
// pfe_set_phy_address_mode(priv->gemac_port,
// CONFIG_PFE_EMAC2_PHY_ADDR,
// PHY_INTERFACE_MODE_RGMII_ID);
// }
break;

[igor_franco]

Hello @yipingwang,

Thank you so much for your answer.

I have already changed the pfe_mdio code to support a fixed link speed and duplex. Once there is no PHY, the auto-negotiation can not be used. Now, with your suggestion, the RGMII communication is working fine. The image below shows the communication through the pfe_eth1 interface (RGMII):

igor_franco_0-1626691480682.png

In green, it is a command to configure the KSZ9477 Switch through I2C. As it is possible to see, after configuring the RGMII in the Switch, I was able to perform a ping. In red, I see a log warning me that the internal MDIO changed from the SGMII port (pfe_eth0) to the RGMII one (pfe_eth1). Could this be a problem to communicate via SGMII? I still can not ping through the SGMII.

Best regards,

Igor

[yipingwang]

In the configuration file "configs/ls1012afrwy_tfa_defconfig", please add the following.

CONFIG_PHY_FIXED=y

[igor_franco]

Hello @yipingwang,

I am already using this configuration option. However, it seems the fixed link only works if it is specified in the DTS. That is a problem once the U-boot DTS does not have a node for PFE. And I have no idea of how the driver is called by the bootloader system. I have put some prints in the code but it is called by the "root driver" (something like that), even without any call in the DTS. It looks like the PFE driver was developed only for communicating with an external PHY. 

Is there some way to use the "fixed-link" PHY in the U-boot DTS? And another question, regarding this topic answer, do I need to configure my SGMII with 1000Base-KX to work without a PHY?

Best regards,

Igor

[igor_franco]

Some extra information.

I compared some register of my custom board with the LS1012A-FRWY. I have found some divergencies between them. The first one is about the SCFG register "PFE PCS status register 1" (PFEPCSSR1). On the Freeway, I have a value of 0x000000c0 (big-endian), indicating the status of the link event and the auto-negotiation (section 11.2.25 of LS1012A Reference Manual). My custom board indicates zero for the same register.

Another difference is regarding the MDIO. I changed the MDIOSELCR (section 11.2.33) to use the internally generated MDIO (value zero) in my custom board. My MDIO appears as a Generic PHY:

igor_franco_1-1626893868447.png

Using the command to read the MDIO status register, I have the following for the LS1012A-FRWY, which has a link-up:

igor_franco_4-1626894102794.png

On the other hand, my custom board is as the following image, without a link:

igor_franco_5-1626894177310.png

I have followed the section 28.7.1.1 instructions to set an SGMII 1G but it still doesn't work. Could those registers indicate some configuration problem? How can I be sure that the MDIO and the PFE are properly configured? What can I do to check if I had some hardware or software issue?

Best regards,

Igor

[yipingwang]

Can you share a block diagram showing how you are connecting LS1012A interfaces to the switch?

[igor_franco · Accepted solution]

Hello @yipingwang,

I will provide you something better: the solution.

I have found the issue regarding the SGMII. The RCW configuration SRDS_REFCLK_SEL, which must be '1', was not set in our custom board file. Also, I have changed the Fixed PHY driver to allow the PFE to use a fixed speed and duplex even without the DTS (as you advise in the previous reply). 

I also changed the pfe_set_mdio function in the eth.c of our board to consider the MDIO name of each GEMAC port:

pfe_set_mdio(priv->gemac_port,
                       miiphy_get_dev_by_name(mac_mdio_info.name));

That avoids the MDIO reconfiguration I sent you in the previous replies. Therefore, I have both SGMII and RGMII working properly now. Just emphasizing that the auto-negotiation was disabled in both devices: the LS1012A processor and the KSZ9477S switch. 

igor_franco_0-1627036627027.png

Now everything is alive. Thank you very much for your support!

I will mark this reply as a solution.

Best regards, 

Igor