LS1012A Single port pfe setting at LSDK

[JYK]

Hi, I want to configure 1-port Ethernet for SGMII communication in LS1012A.

I used the DP8367 phy chip, and configured the PFE of ls1012afrwy.dts as below.

&pfe {

  status = "okay";

  #address-cells = <1>;

  #size-cells = <0>;

  pfe_mac0: ethernet@0 {

  compatible = "fsl,pfe-gemac-port";

  #address-cells = <1>;

  #size-cells = <0>;

  reg = <0x0>; /* GEM_ID */

  fsl,gemac-bus-id = <0x0>; /* BUS_ID */

  fsl,mdio-mux-val = <0x0>;

  phy-mode = "sgmii";

  phy-handle = <&sgmii_phy1>;

fsl,pfe-phy-if-flags = <0x0>;

  };

  /*pfe_mac1: ethernet@1 {

  compatible = "fsl,pfe-gemac-port";

  #address-cells = <1>;

  #size-cells = <0>;

 reg = <0x1>;

  fsl,mdio-mux-val = <0x0>;

  phy-mode = "sgmii";

  phy-handle = <&sgmii_phy2>;

  fsl,pfe-phy-if-flags = <0x1>;

  };*/

  mdio@0 {

  #address-cells = <1>;

  #size-cells = <0>;

  sgmii_phy1: ethernet-phy@2 {

  reg = <0x0>;

  ti,rx-internal-delay = <0x7>;

  ti,tx-internal-delay = <0x7>;

  ti,fifo-depth = <0x1>;

  };

  /*sgmii_phy2: ethernet-phy@1 {

  reg = <0x1>;

  ti,rx-internal-delay = <0x7>;

  ti,tx-internal-delay = <0x7>;

  ti,fifo-depth = <0x1>;

};*/

};

};

However, it seems that the rx packets of eth0 are not being received.

I'd appreciate it if you could let me know if there's anything else I need to set up.

[yipingwang · Accepted solution]

Do you use PHY DP83867? If yes, please configure CONFIG_DP83867_PHY in Linux Kernel configuration file.

In dts file, please replace reg value with your real PHY address on you custom board.

  sgmii_phy1: ethernet-phy@2 {

  reg = <0x0>;///please modify the PHY address with the real PHY address on your custom

  ti,rx-internal-delay = <0x7>;

  ti,tx-internal-delay = <0x7>;

  ti,fifo-depth = <0x1>;

  };

[JYK]

Thanks, I solved the problem that way. But I have another problem, so I would appreciate it if you could also answer the link below.

In LS1012A, reboot in the kernel and RESET on the physical switch do not work well - NXP Community