Issues configuring DDR controller in Baremetal project.

[rhaas]

I have been attempting to configure the DDR controller on a LS1028A dev board made by MYIR. This dev board is based on the NXP LS1028ARDB.

Since the end product is an avionics product, I cannot simply use uboot. I need to prune away code that may not be certifiable with the FAA.

Using uboot as a reference I have initialize the SMMU, TZPC, and CCI400. In addition, I keep the processor at EL3.

I have read the DDR controller registers using uboot. Using the QoriQ DDR configuration tool for the LS series, I imported those registers values. I have generated the bare metal C source code file,  InitDdrRegisters_1.c.

I seem to be able to write to the memory, but reading causes the processor to throw and exception.

I was wondering if anyone may have any idea of what might be missing in the initialization.

[rhaas · Accepted solution]

I just figured out my issue. It turns out that the NXP QorIQ DDR Tool, generates code for baremetal designs does an endian swap on the registers.

I didn’t feel this was odd because the old LS1021A processor that I used before required the endian swap. However the LS1028A processor’s DDR controller is little-endian.

Perhaps, the tool should be changed to not do the endian swap in the InitDdrRegisters_1.c file.

Ray Haas