Hello,
I have designed a custom board using the LS1046A processor and conducted a temperature chamber test. However, when the board temperature reaches around 55°C and the CPU core temperature is approximately 70°C, the board's ASLEEP LED blinks periodically at about 0.5-second intervals, and the system stops functioning.
Additionally, when I connect a console cable, it appears that the system is attempting to reboot repeatedly, as shown in the log below. However, when the temperature decreases, the system resumes normal operation.
I used the LS1046A chip with the highest available temperature rating and referenced the FRWY board for my design.
Are there any debugging steps you would recommend?
(Log attached below)
[2025-03-17 11:39:33.155] NOTICE: Fixed DDR on board
[2025-03-17 11:39:33.592]
[2025-03-17 11:39:33.592] NOTICE: 4 GB DDR4, 64-bit, CL=15, ECC on
[2025-03-17 11:39:33.592] NOTICE: BL2: v1.5(release):LSDK-20.12-dirty
[2025-03-17 11:39:33.592] NOTICE: BL2: Built : 10:47:11, Feb 7 2023
[2025-03-17 11:39:33.867] NOTICE: BL2: Booting BL31NOTICE: BL31: v1.5(release):LSDK-20.12-dirty
[2025-03-17 11:39:33.867] NOTICE: BL31: Built : 10:47:11, Feb 7 2023
[2025-03-17 11:39:33.867] NOTICE: Welcome to LS1046 BL31 Phase
[2025-03-17 11:39:33.867]
[2025-03-17 11:39:33.867]
[2025-03-17 11:39:33.867] U-Boot 2020.04-dirty (Feb 06 2023 - 22:20:05 +0900)
[2025-03-17 11:39:33.946]
[2025-03-17 11:39:33.946] SoC: LS1046A Rev1.0 (0x87070110)
[2025-03-17 11:39:33.946] Clock Configuration:
[2025-03-17 11:39:33.946] CPU0(A72):1600 MHz CPU1(A72):1600 MHz CPU2(A72):1600 MHz
[2025-03-17 11:39:33.946] CPU3(A72):1600 MHz
[2025-03-17 11:39:33.946] Bus: 600 MHz DDR: 2100 MT/s FMAN: 700 MHz
[2025-03-17 11:39:33.946] Reset Configuration Word (RCW):
[2025-03-17 11:39:33.946] 00000000: 0c150010 0e000000 00000000 00000000
[2025-03-17 11:39:33.946] 00000010: 11338888 00400016 40025000 c1000000
[2025-03-17 11:39:33.946] 00000020: 00000000 00000000 00000000 00038800
[2025-03-17 11:39:33.946] 00000030: 20044100 24003000 00000096 00000001
[2025-03-17 11:39:33.946] Model: LS1046A FRWY Board
[2025-03-17 11:39:33.946] Board: LS1046AFRWY-SATURN-HURA, Rev: B, boot from QSPI
[2025-03-17 11:39:33.946] SD1_CLK1 = 100.00MHZ, SD1_CLK2 = 100.00MHZ
[2025-03-17 11:39:33.946] DRAM: 3.9 GiB (DDR4, 64-bit, CL=15, ECC on)
[2025-03-17 11:39:33.955] SEC0: RNG instantiated
[2025-03-17 11:39:34.016] select_i2c_ch_pca9547: Cannot find udev for a bus 0
[2025-03-17 11:39:34.016] Using SERDES1 Protocol: 4403 (0x1133)
[2025-03-17 11:39:34.016] Using SERDES2 Protocol: 34952 (0x8888)
[2025-03-17 11:39:34.016] NAND: 0 MiB
[2025-03-17 11:39:34.016] MMC: FSL_SDHC: 0
[2025-03-17 11:39:34.016] Loading Environment from SPI Flash... SF: Detected mt25qu512a with page size 256 Bytes, erase size 64 KiB, total 64 MiB
[2025-03-17 11:39:34.016] OK
[2025-03-17 11:39:34.016] EEPROM: Read failed.
[2025-03-17 11:39:34.016] In: serial
[2025-03-17 11:39:34.016] Out: serial
[2025-03-17 11:39:34.016] Err: serial
[2025-03-17 11:39:34.016] Net: SF: Detected mt25qu512a with page size 256 Bytes, erase size 64 KiB, total 64 MiB
[2025-03-17 11:39:34.016] Fman1: Uploading microcode version 106.4.18
[2025-03-17 11:39:34.088] PCIe1: pcie@3400000 Root Complex: no link
[2025-03-17 11:39:34.088] PCIe2: pcie@3500000 disabled
[2025-03-17 11:39:34.088] PCIe3: pcie@3600000 disabled
[2025-03-17 11:39:34.088] FM1@DTSEC5, FM1@DTSEC6, FM1@TGEC1
[2025-03-17 11:39:34.088] Error: FM1@TGEC1 address not set.
[2025-03-17 11:39:34.088] , FM1@TGEC2
[2025-03-17 11:39:34.088] Error: FM1@TGEC2 address not set.
[2025-03-17 11:39:34.088]
[2025-03-17 11:39:34.088] Hit any key to stop autoboot: 3 2 1 0
[2025-03-17 11:39:37.144] switch to partitions #0, OK
[2025-03-17 11:39:37.160] mmc0(part 0) is current device
[2025-03-17 11:39:37.176] Scanning mmc 0:1...
[2025-03-17 11:39:37.326] Scanning mmc 0:2...
[2025-03-17 11:39:37.367] Found U-Boot script /ls1046afrwy_boot.scr
[2025-03-17 11:39:38.551] 17635632 bytes read in 1159 ms (14.5 MiB/s)
[2025-03-17 11:39:38.551] do_fpgaload: fpga_load 17635632 bytes in 2591 ms
[2025-03-17 11:39:41.181] 968 bytes read in 17 ms (54.7 KiB/s)
[2025-03-17 11:39:41.181] ## Executing script at 80000000
[2025-03-17 11:39:43.519] 35828224 bytes read in 2333 ms (14.6 MiB/s)
[2025-03-17 11:39:43.558] 31419 bytes read in 17 ms (1.8 MiB/s)
[2025-03-17 11:39:43.798] NOTICE: Fixed DDR on board
[2025-03-17 11:39:44.095] NOTICE: Fixed DDR on board
[2025-03-17 11:39:44.451] NOTICE: Fixed DDR on board
[2025-03-17 11:39:44.861] NOTICE: Fixed DDR on board
[2025-03-17 11:39:45.243] NOTICE: Fixed DDR on board
[2025-03-17 11:39:45.658] NOTICE: Fixed DDR on board
[2025-03-17 11:39:46.047] NOTICE: Fixed DDR on board
[2025-03-17 11:39:46.464] NOTICE: Fixed DDR on board
[2025-03-17 11:39:46.878] NOTICE: Fixed DDR on board
[2025-03-17 11:39:47.282] NOTICE: Fixed DDR on board
[2025-03-17 11:39:47.704] NOTICE: Fixed DDR on board
[2025-03-17 11:39:48.103] NOTICE: Fixed DDR on board
[2025-03-17 11:39:48.530] NOTICE: Fixed DDR on board
[2025-03-17 11:39:48.939] NOTICE: Fixed DDR on board
[2025-03-17 11:39:49.346] NOTICE: Fixed DDR on board
[2025-03-17 11:39:49.754] NOTICE: Fixed DDR on board
[2025-03-17 11:39:50.162] NOTICE: Fixed DDR on board
[2025-03-17 11:39:50.575] NOTICE: Fixed DDR on board
[2025-03-17 11:39:50.991] NOTICE: Fixed DDR on board
[2025-03-17 11:39:51.415] NOTICE: Fixed DDR on board
[2025-03-17 11:39:51.825] NOTICE: Fixed DDR on board
[2025-03-17 11:40:31.984] NOTICE: Fixed DDR on board
[2025-03-17 11:40:32.374] NOTICE: Fixed DDR on board
[2025-03-17 11:40:32.780] NOTICE: Fixed DDR on board
[2025-03-17 11:40:33.190] NOTICE: Fixed DDR on board
The thermal management function is based on TMU (Thermal Monitoring Unit).
The driver sets two thresholds for management function. If the CPU temperature crosses the first one (75 C for LS2080. 85
C for other platforms), the driver will trigger CPU frequency limitation auto-scaling according to the temperature trend; If the
CPU temperature crosses the second one (85 C for LS2080, 95 C for other platforms, critical for core) the driver will shut down the system.