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For data accesses, the Cortex-A53 uses "tends towards exclusive" cache allocation policy:
"Data is allocated to the L2 cache only when evicted from the L1 memory system, not when first fetched from the system. The only exceptions to this rule are for memory marked with the inner transient hint, or for non-temporal loads, see Non-temporal loads, that are only ever allocated to the L2 cache. The L1 cache can prefetch data from the system, without data being evicted from the L2 cache."
For instruction fetches, the Cortex-A53 uses "tends towards inclusive" cache allocation policy:
"Instructions are allocated to the L2 cache when fetched from the system and can be invalidated during maintenance
operations."
It is impossible to modify the this cache policy, this is non-configurable.
Please see
ARM Information Center
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