IFC: GPCM - write in burst mode to async. memory

cancel
Showing results for 
Search instead for 
Did you mean: 

IFC: GPCM - write in burst mode to async. memory

Jump to solution
293 Views
ferdinandgrossm
Contributor III

Hello again.

We're evalutating options to connect a non-volatile memory (nvSRAM, MRAM, FRAM - not flash based) to the LS1046A. One option I'm looking at in more detail right now is the GPCM mode of the IFC and I ran across a question regarding burst access for writing:

Does TCH (chip-select hold time) play a role in burst accesses? And does the write enable signal toggle at all during the burst?

The memory devices we're looking at have an asynchronous SRAM interface, so the IFC_CLK is not used and write accesses are controlled by the chip select and write enable signals. If these don't toggle during burst accesses weÄd need to add some additional logic to insert an additional pulse into the WE or CS signal.

Does anyone have experience connecting asynchronous memory (not flash based)?

Thanks!

Regards

Ferdinand

Labels (1)
Tags (3)
0 Kudos
1 Solution
90 Views
Bulat
NXP TechSupport
NXP TechSupport

Neither WE nor CS toggles during GPCM burst. Yes, you need additional logic to get pulses on those signals. Or optionally you can disable bursts, this affects performance but does not require external logic.

Regards,

Bulat

View solution in original post

2 Replies
90 Views
ferdinandgrossm
Contributor III

Hi Bulat,

thanks for confirming!

0 Kudos
91 Views
Bulat
NXP TechSupport
NXP TechSupport

Neither WE nor CS toggles during GPCM burst. Yes, you need additional logic to get pulses on those signals. Or optionally you can disable bursts, this affects performance but does not require external logic.

Regards,

Bulat

View solution in original post