I work on the LS1046ARDB.
The GIC address is 0x1410000, when chose GIC_ADDRESS_ALIGNED as suggested in the HelloWorld_C_Bare example.
/* GIC alignment (only valid for GIC_VER = 2)
* For LS1046A, LS1026A, LS1043A (rev. 1.1), LS1023A (rev. 1.1) set this to 1.
*/
#define GIC_ADDRESS_ALIGNED 1
#if GIC_ADDRESS_ALIGNED == 0
#define CONFIG_ARM_GICD_BASE_OFFSET 0x1000
#define CONFIG_ARM_GICC_BASE_OFFSET 0x2000
#else
#define CONFIG_ARM_GICD_BASE_OFFSET 0x10000
#define CONFIG_ARM_GICC_BASE_OFFSET 0x2F000
#endif
#define CONFIG_ARM_GIC_BASE_ADDRESS 0x1400000
While the GIC has the base address is 0x1401000 in Peripherals view, so all the registers are always zero.
Please refer to the following in u-boot source code arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S.
/* Get GIC offset
* For LS1043a rev1.0, GIC base address align with 4k.
* For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
* is set, GIC base address align with 4K, or else align
* with 64k.
* output:
* x0: the base address of GICD
* x1: the base address of GICC
*/
ENTRY(get_gic_offset)
ldr x0, =GICD_BASE
#ifdef CONFIG_GICV2
ldr x1, =GICC_BASE
#endif
#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
ldr x2, =DCFG_CCSR_SVR
ldr w2, [x2]
rev w2, w2
lsr w3, w2, #16
ldr w4, =SVR_DEV(SVR_LS1043A)
cmp w3, w4
b.ne 1f
ands w2, w2, #0xff
cmp w2, #REV1_0
b.eq 1f
ldr x2, =SCFG_GIC400_ALIGN
ldr w2, [x2]
rev w2, w2
tbnz w2, #GIC_ADDR_BIT, 1f
ldr x0, =GICD_BASE_64K
ifdef CONFIG_GICV2
ldr x1, =GICC_BASE_64K
#endif
1:
#endif
ret
ENDPROC(get_gic_offset)