How to update CPLD in TWR-LS1021A under Ubuntu

[shuodo]

Hi,

How can I update CPLD in TWR-LS1021A board under Ubuntu?

I can find the "twr_ls1021a_cpld.v and TWR_LS1021A_CPLD_v3.3_1129.jed" CPLD files under CPLD folder of your Hardware package.

Thanks,

Shuo

[ufedor]

You wrote:
> How can I update CPLD in TWR-LS1021A board under Ubuntu?
There is no way to do that. 

You wrote:

> Is it possible that CPLD could be overwritten or corrupted?

For the CPLD programming dedicated external tool has to be used - please refer to the:
http://www.latticesemi.com/programmer

> I tried both NOR boot and SD boot.

Please explain in detail what you have done.

Do you have CodeWarrior and CodeWarrior TAP to debug the board?

[shuodo]

Hi,

Regarding NOR boot and SD boot, this is what I did:

TWR-LS1021A board has its original image in NOR. And I didn't touch

anything in NOR, so leave it as it is.

Then, I have prepared my own image + kernel + u-boot in an SD card using

NXP linux SDK. I changed the SW settings so that it will boot from SD card

instead of NOR. And it worked.

Basically, I can change the SW settings to boot from the original image in

NOR, or my own image in SD card.

But after boot failure issue happened, it cannot boot from any of them.

I don't have CodeWarrior TAP hardware to debug my board. I haven't

purchased yet.

But I do have a J-Link debugger. I was using openOCD with an auto-probe

openOCD config file.

J-Link debugger + openOCD auto-probe used to work before. It can detect all

TAP target on TWR board.

But after boot failure issue happened, it no longer can detect any TAP on

TWR board.

Thanks,

Shuo

[ufedor]

Please check that all on-board supply voltages have correct values.

Please try complete SD card firmware image from the NXP LSDK available at:

LSDK Open Source 

section LSDK IMAGES.

[shuodo]

Hi,

No, it still not able to boot up after re-program SD card.

The voltage level is correct.

I think the issue is caused by CPLD. Suppose the steps when I program SD card was wrong. TWR should at least boot from NOR where stores the original image. But NOR boot doesn't work either. CPLD is critical in TWR because it controls the power-on-reset signal to the processor.

The CPLD registers maps to 0x7FB0_0000 - 0x7FB0_FFFF. If I mistakenly write in this address space, will CPLD image get corrupt? I mean is it possible to corrupt CPLD image on TWR?

Thanks,

Shuo

[ufedor]

> If I mistakenly write in this address space, will CPLD image get corrupt?

No.

> I mean is it possible to corrupt CPLD image on TWR?

This is impossible.

Please check that clock is provided for the CPLD.

[shuodo]

Hi,

After I keep the power plugged in for about 10 minutes, it successfully boot up. After the first time long wait boot up, it can boot up immediately after plug in power.

I don't know what happened.

Thanks,

Shuo

[ufedor]

Similar issue was not reported by other customers.