How to configurate ethernet in Device Tree for own board with LS1021a?

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How to configurate ethernet in Device Tree for own board with LS1021a?

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Contributor II

Hi there!

I have a problem with my new developed LS1021a Board. There are three ethernet PHYs connected to LS1021a. Two PHYs are connected via SGMII with the PHY-Adresses 1 and 2. The third PHY is connected via RMII and comes with address 3. The source from U-Boot, especially the ls1021a-twr was modified for this and the compiled U-Boot is running fine. I can ping a server from all ethernet ports. But! If i boot my linux kernel with Rootfilesystem and device tree, i can't connect with the interfaces anymore. The kernel-messages informs me, if i have a connection on a ethernet-port like: "libphy: mdio@2d24000:02 - Link is Up - 100/Full" So that is working, too.

The ls1021a.dtsi is from scratch and i didn't touch it. Actually i modify the ls1021a-twr.dts... Maybe i have a mistake in my code? :

aliases {

  enet2_rmii_phy = &rmii_phy3;

  enet0_sgmii_phy = &sgmii_phy1;

  enet1_sgmii_phy = &sgmii_phy2;

  };

&enet0 {

  tbi-handle = <&tbi1>;

  phy-handle = <&sgmii_phy1>;

  phy-connection-type = "sgmii";

  status = "okay";

};

&enet1 {

  tbi-handle = <&tbi1>;

  phy-handle = <&sgmii_phy2>;

  phy-connection-type = "sgmii";

  status = "okay";

};

&enet2 {

  phy-handle = <&rmii_phy3>;

  phy-connection-type = "rmii-id";

  status = "okay";

};

&mdio0 {

  sgmii_phy1: ethernet-phy@1 {

  reg = <0x0>;

  };

  rmii_phy3: ethernet-phy@3 {

  reg = <0x2>;

  };

  sgmii_phy2: ethernet-phy@2 {

  reg = <0x1>;

  };

  tbi1: tbi-phy@1f {

  reg = <0x1f>;

  device_type = "tbi-phy";

  };

};

Can you help me please? Thank you very much

Jan Brand

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181 Views
Contributor II

Hi Jan!

I have the similar problem with our new developed LS1020 Board. There are three ethernet PHYs connected to LS1020a. Two PHYs are connected via RGMII with the PHY-Adresses 1 and 3.

I can not ping the server from U-boot and from Roorfilesystem.

Could you explain how you modified the U-boot in order to ping ?

We use the LS1021A-IOT board as the reference board. We changed the RCW values: EC1=000 and EC2=000.

Regards

Victor

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Contributor II

Hi Victor,

For the PHY-Adresses you can change the header-file for your board under the u-boot source directory. I used the ls1021atwr.h in the bootloader repository include/configs/

There I changed the PHY-Adresses:

/*

* eTSEC

*/

#define CONFIG_TSEC_ENET

#ifdef CONFIG_TSEC_ENET

#define CONFIG_MII

#define CONFIG_MII_DEFAULT_TSEC 1

#define CONFIG_TSEC1 1

#define CONFIG_TSEC1_NAME "eTSEC1"

#define CONFIG_TSEC2 1

#define CONFIG_TSEC2_NAME "eTSEC2"

#define CONFIG_TSEC3 1

#define CONFIG_TSEC3_NAME "eTSEC3"

/* commended out the old stuff:

#define TSEC1_PHY_ADDR 2    

#define TSEC2_PHY_ADDR 0

#define TSEC3_PHY_ADDR 1

*/

#define TSEC1_PHY_ADDR 1

#define TSEC2_PHY_ADDR 2

#define TSEC3_PHY_ADDR 3

Is that, what you're looking for?

kind regards,

Jan

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Contributor II

Hi Jan,

Thank you for your answer.

Our board, based on the LS10210E processor, has three Ethernet transceivers. First transceiver is connected to the CPU through TSEC1_RGMII Module. Its Ethernet PHY address is 1. Second transceiver is connected to the CPU through TSEC2_RGMII Module. Its Ethernet PHY address is 3. I would like to adapt the U-boot and Linux Kernel for Ethernet communication.

We adjusted the RCW file (EC1=000 and EC2=000). However the U-boot application displays errors:

Phy 1 not found

PHY reset timed out

Phy 3 not found

PHY reset timed out

I am looking for how to modify the U-boot code in order to fix these errors.

Regards

Victor Mazin

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NXP TechSupport
NXP TechSupport

Can you please share the following materials/information:

1. Your Device Tree blob binary (DTB)

2. Full console log, including all messages generated during boot and initialization, all your diagnostic commands

    and the reaction of the system to them.

3. The version of QorIQ SDK you are working with.

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Contributor II

Yes for sure:

1. myboard.dtb -Device Tree Blob

2. log.txt -Console Log 

3. Version of QorIQ SDK is 1.9, but I'm using only the kernel from it for my board. Rootfilesystem is created with PTXdist.

Thank you and kind regards

Jan

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181 Views
Contributor I

Did this issue get resolved?

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181 Views
Contributor II

no, it is still not.... Can anyone give me an advise?

kind regards,

Jan

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