How to check the DDR access timing with JTAG?

[tomo]

I want to check DDR access timing of the LS1046A is correct with JTAG debugger.

The DDR validation tool seems to change the registers of CLK_ADJUST and WRLVL_START to determine whether the timing is correct, but can you do the same with JTAG?

I tried changing those registers with the JTAG debugger, but no matter what value I set, the access to the DDR memory did not become abnormal.

In order to check the setting value, can I only use the DDR validation tool?

Best regards,

tomo.

[ufedor · Accepted solution]

You wrote:

> I tried changing those registers with the JTAG debugger

Please note that the training sequence is performed by the DDR controller only once - after the DDR_SDRAM_CFG[MEM_EN] is set.

So the timing values in question have to be set before the MEM_EN setting - else the change will not be detected by the DDR controller.

To test the values it is possible to recompile U-Boot with new timing values, program the binary image into flash and boot.