We are having a custom board with LS1021A-TWR processor. SRAM is connected on IFC bus with chip select 2. We need to access SRAM through MTD.
For this I have made some changes in dts as shown below.
#address-cells = <2>;
#size-cells = <1>;
/* NOR Flash on board and SRAM */
ranges = <0x0 0x0 0x0 0x60000000 0x08000000>
<0x2 0x0 0x0 0x7e800000 0x00080000>;
status = "okay";
compatible = "mtd-ram";
reg = <0x2 0x0 0x80000>;
bank-width = <2>;
compatible = "fsl,ls1021atwr-cpld";
reg = <0x2 0x0 0x100>;
The driver for the SRAM chip registers the device as a MTD.
~# cat /proc/mtd
dev: size erasesize name
mtd0: 00080000 00001000 "7e800000.sram"
But use of echo > and cat to the mtdblock results garbage.
Is there any changes required in kernel and u-boot side?
Not able to access SRAM under uboot. We don't have a clock in SRAM(IS62WV25616EBLL). In this case how to calculate the flash timing register values(need to configure in ls1021atwr.h file)?