Disable AIOP and QBMAN and increase RESMEM in LS2044A based custom board

[priyadharshinik]

Hi,

In our custom board based on LS2044A, we have one Management ethernet port connected. 

DPAA2 Reserved Memory of 2GB(mcmemzize ~7.5GB) is reserved.

We would need to reduce the mcmemsize to 128KB and use the avaialble memory for User application. 

How do we disable AIOP/QBMAN and reduce the mcmemsize to 128KB ?

[yipingwang]

By design u-boot doesn't modify MMU entries at runtime, for changing mcmemsize to take effect you need to saveenv and reboot.

So what you need to do is as the following in u-boot.

=> pri mcmemsize

mcmemsize=0x70000000

=> setenv mcmemsize 0x40000000

=> saveenv

=> reset

Before modifying mcmemsize

root@TinyLinux:~# cat /proc/meminfo

MemTotal:       14231844 kB

MemFree:        13595336 kB

After modifying mcmemsize to 0x40000000.

root@TinyLinux:~# cat /proc/meminfo

MemTotal:       15261984 kB

MemFree:        14623404 kB

[priyadharshinik]

Thanks for your response.

Yes, I can reduce mcmemsize environmental variable to “0x40000000” (1GB).

But as mentioned, we are using only one management port in our current design.

So we still want to reduce the mcmemsize to “0x8000000” (128MB) and use the rest of the memory for application.

But when we reduce the mcmemsize to 0x8000000 (128MB), we are getting below error in u-boot while loading MC firmware.

fsl-mc: Booting Management Complex ... WARNING: Firmware returned an error (GSR: 0xd)

fsl-mc: Management Complex booted (version: 10.20.4, boot status: 0xd)

Here is the reference from DPAA2 user manual. As per the below given table, we would want to disable  QBMAN and AIOP and check if mcmemsize of 128MB works and MC firmware gets loaded properly in uboot.

So, Please help on how to reduce mcmemsize to 128MB .

[yipingwang]

I downloaded LS2088ARDB NOR flash firmware image of LSDK 20.12 and deploy it on LS2088ARDB, I configured mcmemsize as 0x8000000 successfully.

$ wget https://www.nxp.com/lgfiles/sdk/lsdk2012/firmware_ls2088ardb_uboot_norboot.img

Under u-boot on LS2088ARDB

=> pri mcmemsize
mcmemsize=0x70000000
=> setenv mcmemsize 0x8000000
=> saveenv
Saving Environment to Flash... Un-Protected 2 sectors
Erasing Flash...
.. done
Erased 2 sectors
Writing to Flash... 9....8....7....69....8....7....6....5....4....3....2....1....done
Protected 2 sectors
OK
=> reset
resetting ...
=
▒NOTICE: UDIMM 18ASF1G72AZ-2G3B1

NOTICE: 16 GB DDR4, 64-bit, CL=13, ECC on, 256B, CS0+CS1
NOTICE: UDIMM 18ASF1G72AZ-2G3B1

NOTICE: 4 GB DDR4, 32-bit, CL=11, ECC on, CS0+CS1
NOTICE: BL2: v1.5(release):LSDK-20.12
NOTICE: BL2: Built : 04:35:48, Dec 11 2020
NOTICE: BL31: v1.5(release):LSDK-20.12
NOTICE: BL31: Built : 04:35:48, Dec 11 2020
NOTICE: Welcome to LS2088 BL31 Phase

U-Boot 2020.04-gf46a944f71 (Dec 11 2020 - 04:35:39 +0800)

SoC: LS2088AE Rev1.1 (0x87090011)
Clock Configuration:
CPU0(A72):1800 MHz CPU1(A72):1800 MHz CPU2(A72):1800 MHz
CPU3(A72):1800 MHz CPU4(A72):1800 MHz CPU5(A72):1800 MHz
CPU6(A72):1800 MHz CPU7(A72):1800 MHz
Bus: 700 MHz DDR: 1866.667 MT/s DP-DDR: 1600 MT/s
Reset Configuration Word (RCW):
00000000: 483038b8 48480048 00000000 00000000
00000010: 00000000 00000000 00a00000 00000000
00000020: 01e01180 00002581 00000000 00000000
00000030: 00400c0b 00000000 00000000 00000000
00000040: 00000000 00000000 00000000 00000000
00000050: 00000000 00000000 00000000 00000000
00000060: 00000000 00000000 00027000 00000000
00000070: 412a0000 00040000
Model: Freescale Layerscape 2080a RDB Board
Board: LS2088AE Rev1.1-RDB, Board Arch: V1, Board version: F, boot from vBank: 4
FPGA: v1.22
SERDES1 Reference : Clock1 = 156.25MHz Clock2 = 156.25MHz
SERDES2 Reference : Clock1 = 100MHz Clock2 = 100MHz
DRAM: 15.9 GiB
DDR 15.9 GiB (DDR4, 64-bit, CL=13, ECC on)
DDR Controller Interleaving Mode: 256B
DDR Chip-Select Interleaving Mode: CS0+CS1
SEC0: RNG instantiated
SEC0: RNG instantiated
Using SERDES1 Protocol: 42 (0x2a)
Using SERDES2 Protocol: 65 (0x41)
Flash: 128 MiB
NAND: 2048 MiB
MMC: FSL_SDHC: 0
Loading Environment from Flash... OK
EEPROM: Invalid ID (ff ff ff ff)
In: serial
Out: serial
Err: serial
Net: PCIe1: pcie@3400000 disabled
PCIe2: pcie@3500000 disabled
PCIe3: pcie@3600000 Root Complex: x1 gen1
PCIe4: pcie@3700000 Root Complex: no link
e1000: 68:05:ca:3f:90:55
DPMAC1@xgmii [PRIME]
Warning: DPMAC1@xgmii (eth0) using random MAC address - ca:55:8f:d9:f4:3c
, DPMAC2@xgmii
Warning: DPMAC2@xgmii (eth1) using random MAC address - 12:06:7d:99:58:fa
, DPMAC3@xgmii
Warning: DPMAC3@xgmii (eth2) using random MAC address - b6:9a:e3:2f:ee:54
, DPMAC4@xgmii
Warning: DPMAC4@xgmii (eth3) using random MAC address - aa:db:4e:25:4e:9c
, DPMAC5@xgmii
Warning: DPMAC5@xgmii (eth4) using random MAC address - d6:ce:41:8e:5b:0a
, DPMAC6@xgmii
Warning: DPMAC6@xgmii (eth5) using random MAC address - f2:ae:70:ee:cb:da
, DPMAC7@xgmii
Warning: DPMAC7@xgmii (eth6) using random MAC address - 76:33:2b:17:ac:a4
, DPMAC8@xgmii
Warning: DPMAC8@xgmii (eth7) using random MAC address - 5a:66:bb:3e:f2:01
, e1000#0
crc32+
fsl-mc: Booting Management Complex ... SUCCESS
fsl-mc: Management Complex booted (version: 10.24.0, boot status: 0x1)
Hit any key to stop autoboot: 0
=> pri mcmemsize
mcmemsize=0x8000000
=>

[priyadharshinik]

Thanks for the response.

I have set mcmemsize to 128MB  and mcmemsize environment variable is updated.

But still, 512MB is reserved, when i checked "bdinfo" in uboot.

Is it because of SYS_MC_RSV_MEM_ALIGN set to default 0x2000000 (512MB) in drivers/net/fsl-mc/Kconfig?

If I change that to 128MB, would 128MB memory be reserved?

Do you advice to change the above config and reserve 128MB for MC or minimum 512MB needs to be reserved?

In DPAA2 Manual, minimum memory requirement is “128MB” for LS2044A based architectures..

So, we would like to reduce the reserved memory to 128MB and use rest of the RAM for application.

And we want to make sure, we are able to connect to multiple ssh connections and ethernet management interface works fine with 128MB reserved.

Please suggest…

[yipingwang]

You could configure SYS_MC_RSV_MEM_ALIGN in drivers/net/fsl-mc/Kconfig to 128M.