Please reference our developer.arm.com website for the information that is mentioned below:
In order to access PMU, as mentioned <DDI0500F_cortex_a53_r0p4_trm.pdf>
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12.2.4 PMU register interfaces The Cortex-A53 processor supports access to the performance monitor registers from the internal system register interface and a memory-mapped interface. External access to the performance monitor registers is also provided with the APB slave port.
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Hence, to access PMU through internal system register, for example:
From TRM, it provides an example.
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To access the PMCR in AArch32 Execution state, read or write the CP15 registers with: MRC p15, 0, <Rt>, c9, c12, 0; Read Performance Monitor Control Register MCR p15, 0, <Rt>, c9, c12, 0; Write Performance Monitor Control Register
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And if you wish to access PMU register through APB slave port, then you would reference <DIT0036E_cortex_a53_r0p4_im.pdf> section 4. In that section, it guides customer to integrate CA53 with coresight subsystem. And please reference <coresight_soc400_user_guide_100490_0302_01_en.pdf> section 7.8.1 cssys_upv8 example system, it shows that key path that made it possible to have internal route to access CA53's APB slave port.
Its key block diagram is attached. As you can see there exist an internal path:
Processor --> AXI --> NIC--> system APB --> cxapbic --> CA53;s Debug APB slave port.
Hence, when you have CA53 integrate with coresight subsystem, the above path
Would be the way to access PMU through CA53 APB slave port.
