Hi all,
I am in the process of trying to bring up a LS1046A board. Its a custom board based heavily off the Freeway design. The first step I am trying to do is get the connection diagnostics to pass with RCW override and DDR settings. D_INIT is cleared and its gets to the DDR memory access test. However when checking logs I can see that the DDR values do not match their expected values. See picture and logs(Read_Write_mem.txt). I see some resemblance of the expected values. D_Init_value is set to 0xDEADBEEF.
Some things we tried and validated:
Hardware:
- Schematics reviewed and double checked
- Voltages are checked. GVDD, VREF, VTT and VPP
- Input and output DDR clocks
- DRAM reset signal is correct
- MEM enable signal is correct
Software:
- RCW correct and double checked. See below
- DQS skews are correct and double checked with schematics
- DQ mapping should be correct. Using the exact same layout as the Freeway board. See attached.
I am unable to find a DDR config for the Freeway board. Is this something we can get to compare to our settings? Any pointers to what might be wrong? Im assuming its settings related since D_INIT is cleared and we are actually able to read/write to DDR.
You can also find the logs below for the test for centering the clocks. Its ran with RCW override with the RCW mentioned below. CCS Output is also added.
RCW:
RCWSR1:0x0810000d
RCWSR2:0x0a000000
RCWSR3:0x00000000
RCWSR4:0x00000000
RCWSR5:0x00000000
RCWSR6:0x40000002
RCWSR7:0x40000000
RCWSR8:0xc1000000
RCWSR9:0x00000000
RCWSR10:0x00000000
RCWSR11:0x00000000
RCWSR12:0x00000800
RCWSR13:0x00000000
RCWSR14:0x00000000
RCWSR15:0x00000096
RCWSR16:0x00000001
Any tips and/or pointers to potential fixes is appreciated.
Rinke
