DDR initialization fails on a cusotom board based on LS1028A

[pb3]

Hi, we've been trying to bring-up DDR on our custom board based on LS1028A.

We do not use SPD, we have 5 discrete (4 + ECC) modules soldered on the board.

The memory we've been using is IS43QR85120B-083RBLI

Below are trace lenghts on our PCB for each module.

The RCW has been taken from LS1028A-RDB.

For some initial testing, we've added support in TF-A for our board with ddr_init returning -1 just to see if anything works - indeed it works, we are able to reach this step, we see logs printed out on the console.

Below some of the information about our PCB

DQS Length CK [mm] Length DQS [mm] Difference (CK - DQS) [mm] Rounded Difference [mm]

DQS0

62.50715

44.20325

18.30390

18

DQS1

76.64270

33.37230

43.27040

43

DQS2

91.49900

30.91965

60.57935

60

DQS3

105.84010

30.60260

75.23750

75

DQS8

120.28730

36.08540

84.20190

84

DDR Wizzard configuration settings:
- autoconfigruration

- discrete DRAM

- Type: DDR 4

- Rank/Chip select: 1

- tCL: 11 clocks

- ECC (disabled for the purpose of 1st step of DDR validation)

- DRAM configuration 4Gb: 512Mb x8

- DRAM speed rating: 1600 MT/s

- CLKS to DQS (values are negative as our DQS lines are shorter that CLK)

  - 18, -43, -60, -75 (ECC skipped for now)

Once the Wizzard has been finished, I manually changed DQ mapping to match the signal routes on our board.

The problem is that literally none of the validation steps pass.

I would be grateful if anyone could give me some hint, where we should look for source of our problems.

[pb3]

One more thing - we in fact use LS1027A, but I don't think it's much difference in this context.

[yipingwang]

A1: CLK to DQS skew can be negative value or positive value.

A2: only need to load RCW/PBL image before running QCVS.  DQ mapping is read from SPD for DIMM or is set manually as per the board layout for the discrete DRAM.

A3: If your board is very similar with LS1028ARDB with the same DDR rate, it's ok to use the same settings of RCW, otherwise, the settings of your RCW should be consistent with your board design.

A4: DDR_ERR_DETECT[ACE] bit set with the message "Validation cannot proceed due to other DDR hardware or software issues!" may be caused as these:

    - The training sequence DDRC follows to calibrate the read data path was not able to complete. This would probably only happen if there was a hard failure on the memory interface caused by board-level issues or incorrect controller settings.

    - Incorrect termination of MDICx signals.

    - Write leveling calibration was not able to complete. This relates to improper settings of the DDR_WRLVL_CNTL register or board-level issues.

DDR timging parameters include different aspects:  DRAM-specific timing parameters (from DRAM data sheet) and board-specific timing parameters.

Before running QCVS validations, it needs set many proper timing parameters in Properties tab of QCVS tool.

e.g.  - DQ_mapping lanes setting (depend on board design).

        - tCL, tRCD, tRP, tRAS specified usually as tCL-tRCD-tRP-tRAS. These timings are measured in bus clock cycles on the custom board for discrete DRAM (or read from SPD for DIMM).

        - tWR, tRRD, tWTR, etc. These timings are set as per the DRAM data sheet.

The board-specific timing parameters can be optimized by QCVS Validations, then update these parameters in atf/plat/nxp/soc-ls1028/ls1028axxx/ddr_init.c.

[pb3]

Just forgot to mention, most tests end with ERR_DETECT -> ACE error 0x00000001

[yipingwang]

Please refer to DDRv user manual https://www.nxp.com/docs/en/user-guide/QCVS_DDR_User_Guide.pdf

If the customer uses Discrete DDR, in DDR configuration panel, please select “Configuration mode” as “Auto configuration” and “Discreate DRAM”, and configure board and DDR controller related settings according to the custom board. Then in the project, please configure DDR related configuration parameters in “properties” panel according to the DDR data sheet.

[pb3]

Hi yipingwang, thanks for the response!
I've browsed this document many times as well as watched one of the videos you've recorded, but still I'm unsure about few things.
I would be glad if you could answer few of my questions:
- what if my DQS lines are longer than CLK? Should I put negative values in CLKS to DQS boxes during the DDR wizzard?
- do I need to load any image for the purpose of DDR validation, besides the PBL? In other words, if I e.g. change DQ mapping, is QVCS able to program the required registers during the validation?
- If our board is very similiar to ls1028ardb - at least looking at the RCW I really don't see major difference (pin muxing may be different), can I just read PBL from LS1028ARDB and use it for the purpose of DDR validation on my board?
- I've browsed through some topics on the forum, and I noticed that someone had similiar problem with ERR_DETEC ACE, and one of your collegues asked about HRESET and DDR reset relation (https://community.nxp.com/t5/QorIQ/How-to-bring-up-the-DDR-controller-in-the-LS1046A/m-p/728369/high...) is it relevant for LS1028a based boards? May it be the source of ERR_DETECT ACE errors during validation or is it rather not relevant?

[pb3]

We corrected our DDR Reset it now follows HRESET, however the issue remain the same. We constantly see ACE error being raised in each step of validation. None of the steps succeeded.
We double-checked DQ mapping and it matches as expected.
What else should we check?

[yipingwang]

Discussing with the AE team.