Hi Pavel,
Table 32-2 refers to OOB timing specifications for the SATA interface, is this the correct table number? I'm not seeing PCIe enable bits in the RCW settings either.
I'm also seeing a similar issue when enabling the MMU and Cache with the following code:
__asm__ __volatile__ (
"mrc p15, 0, r0, c1, c0, 0;" /* Read SCTLR into R0 */
"orr r0, r0, #0x4;" /* Set C bit (bit 2) in SCTLR value */
"orr r0, r0, #0x1000;" /* Set I bit (bit 12) in SCTLR value */
"orr r0, r0, #0x1;" /* Set M bit (bit 0) in SCTLR value */
"mcr p15, 0, r0, c1, c0, 0;" /* Write configuration to SCTLR register */
);