CodeWarrior Hareware Diagnosis Walking Ones Memory Test Failure LS1021a

[jiye]

Hi,

I recently performed a memory test for the hardware eMMC of my ls1021a as well as LS1021a-TWR SD card.

Anyone knows what's going on here ? It kept failing I did not know why it's expecting some values for example 0X7F but instead 0XCC, I thought it suppose to be initialize all values to 0s first then perform the test but seems like it's not the case.

[alexander_yakov]

Memory tests are intended to be used with RAM-type memories (volatile memories), where the number or read/write operations is not limited, and memory interface is parallel (for higher bandwidth). Every memory test type is effective against it particular defect type. For example, "Walking ones" test. In this test you write all memory with 00000001 and than read back to check, and rotate this pattern in cycle. This memory test is used to test data bus line, assuming your data bus connection to memory is parallel bus.

In eMMC case, there is no parallel data bus, so - no need to test it with walking ones. Also, eMMC memory is flash-type memory, it has limited number of writes, as any other flash. Continious write and read the same memory cell may damage this memory. So, testing flash-type memory with standart memory tests is not recommended. 

[jiye]

how could I test my RAM if the only way I can establish the communication between my board and Codewarrior is via the OCRAM?

Also by saying testing the RAM you mean I change the value here

to 0x80000000?  since 80000000 is the RAM

Still has error:

[alexander_yakov]

Before running memory test, the memory must be enabled and initialized in memory controller registers. As a part of this initialization, memory base address and size is configured. If the board is running under CodeWarrior control, this is performed in target initialization file. Common RAM (DDR memory) usually starts at 0x00000000, however this starting address is configurable in target initialization file. So, please refer to your CodeWarrior target initialization file for memory starting address.

[jiye]

But the LSDK1906 says 0x8000_0000

[alexander_yakov]

Yes, specifically for LS1021A processor DRAM starts at 0x80000000 (region 1, 2GB size). Starting address 0x00000000 is used for Secure boot ROM. The same is said in LS1021A Reference Manual, Table 2-1 "System memory map"

[jiye]

then my question comes to is my ls1021a customized board has the same DDR address mapping? If so then I can use the same init configuration files without changing anything right I meant if it works on the EVA board it should work on my customized board as well.

(2) if (1) is the same, how do I ensure it would be the same as EVA's memory mapping, should be a concern from hardware design's perspective right?

[alexander_yakov]

Yes, if your customized board has the same memory parts, connected in the same way, than you can try using the same target initialization script on your custom board. Yes, it is recommended to use the same memory mapping. 

[jiye]

I have 2 4GB DDR3 connected instead of only one as EVA board does. i don't think they are the same as EVA?

(2) I have the access into the my board now from serial console but it shows 1 GB of DDR in the uboot but I have 4 GB DDR what is the issue here, also when I perform free -m in the linux I saw only 1GB DDR available as well.

[alexander_yakov]

1. Yes, if you have two memory chips instead of one used on our development board, than this means target initialization file for our development board is not directly applicable for your custom board, and some changes in memory settings are required.

2. U-boot uses its own settings, it does not use CodeWarrior target initialization file. So, U-boot memory configuration settings should be also updated to accomodate new memory configuration.

[jiye]

I confirmed it's only one 4GB DDR, all connections are the same how do I do it in the uboot to accommodate  new memory configuration?

[alexander_yakov]

This question is quite far from the initial issue of this topic, please create a new topic for this question.

[jiye]

(1)"must be enabled and initialized in memory controller registers" which target initialization file you are talking about here

[alexander_yakov]

When the processor comes out of reset, it has all its internal registers cleared (or set to defaut after-reset values). As a part on initial boot process, the boot loader initializes processor registers with specific (non-default) values. For example, if you wish to access external memory, you have to configure processor' onchip memory controller with settings, specific to your external memory (memory starting address, size, row/column size, cas latency end etc). This is usually done by bootloader. 

However, in case when the procesor is running under debugger control, the debuger if able to bring up the processor even if there is no boot loader in processor onboard flash. In this case, all necessary register initialization steps are performed by debugger itself, using the information from special "target initializatin file", specified in debugger connection settings. For our boards, supported by CodeWarrior, we distribute target initialization files as a part of CodeWarrior, in CodeWarrior installation folder.     

[jiye]

Speaking to the file called LS1021A_TWR_Init.tcl

Can you tell me what are these addresses stand for?

[alexander_yakov]

Addresses like "0x01080110" are addresses of memory mapped registers. In this case, "110" is register offset, this particular number corresponds to register DDR_SDRAM_CFG. The offset is from base address 0x01080000, which is base address of DDR controller. Please look LS1021A Reference Manual, Section 16.4.1 for details.

To determine the base address of DDR memory device, connected to fisrt chip select line, you should look register CS0_BNDS (address 0x01080000), this register contains two values - starting and ending address. First 16 bits of this register ("0080") are 16 most significant bits of 40-bit address. That is, full address is 0x0080000000. For more details, please look LS1021A Reference Manual, Section 16.4.2 

[jiye]

in other words, I need establish the communications between my CPU and CW via RAM instead of OCRAM?

[alexander_yakov]

Communitaction between CPU and CodeWarrior debugger is performed via debug interface, which is a part of processor. Communication is performed directly, but not via RAM or OCRAM, and can be performed even if no RAM or OCRAM available.