CW TAP Failed to write memory at address 0x70007002c on core CortexA72#0

[xmj]

Hi, 

We develop a custom board based on LX2160A. We meet the problem of failing to run target initializaton script with CW TAP during the diagnose connetiong period after power on reset. Is there any way to debug this issue?

Thanks.

[ankur29]

Hi, I also got the same error while trying hardcore reset, this issue started from my flash secure xspi image and the reset after that board stuck and past 2 days, I cannot able to access the board nor I able to flash new firmware.

Board LA1224rdb_revc

Memory access failed.
//
Additional error details:
[Failed to write memory at address 0x70007002c on core CortexA72#0.
Core CortexA72#0 not found on the JTAG chain. Please verify that the Reset Configuration Word is correct, or enable RCW Override in the initialization file.]

[ufedor]

It is required to use QCVS DDR Validation Tool to determine parameters for the custom board and modify the initialization script accordingly.

[xmj]

Hi ufedor,

Thanks for your reply. 

Update: After updating RCW on SPI NOR flash and the board initialization script, I received DDR PHY 1D Training error.  

[xmj]

After correcting the RCW for the custom board, the "Failed to write memory at address xxx on core CortexA72#0" error no longer exist. But we got some new error message during the DDR validation period with QCVS DDR Validation Tool.  Any idea about this issue? Here is the error message:

#################### Result for: ddr_vref_searcher ###### Run 1 ###################################

Test result: [
<<Test failed!>>
{{ERROR: Error occurred in Python command: "monitor run :ccs:LX2160A:CortexA72#0" failed.
//
Additional error details:
[GTA: context not found]
}}

]
[0x7FF83D50E0A4] ANOMALY: use of REX.w is meaningless (default operand size is 64)

[ufedor]

The error can be interpreted so that JTAG chain does not contain any of the A72 cores. So QCVS tool might not be able to run code (DDR PHY driver) on the target. Please double check with CCS that the chain can be correctly configured and the cores are correctly identified.

Also make sure that CW (debugger) and QCVS tool are up-to-date.

[xmj]

We tried to determine parameters for the custom board with QCVS DDR Validation Tool, but it occures the "Failed to read memory from address 0x1080bf8 on core CortexA72#0" issue.