I am running pre-layout signal integrity simulations on the LS1046A PCIe lanes, and was looking for guidance on BGA breakout routing dimensions (worst-case) to use in HyperLynx. I'm currently assuming 6 mil trace width and 4 mil space, with a max length of 700 mils on the surface before the DC blocking capacitor (on the transmit side) and to a via to an internal layer. I don't know if I should assume a narrower trace width due to the BGA congestion.
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