BGA breakout routing dimensions, LS1046

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BGA breakout routing dimensions, LS1046

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Contributor II

I am running pre-layout signal integrity simulations on the LS1046A PCIe lanes, and was looking for guidance on BGA breakout routing dimensions (worst-case) to use in HyperLynx. I'm currently assuming 6 mil trace width and 4 mil space, with a max length of 700 mils on the surface before the DC blocking capacitor (on the transmit side) and to a via to an internal layer. I don't know if I should assume a narrower trace width due to the BGA congestion.

Thanks.

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NXP TechSupport
NXP TechSupport

It is possible to refer to the LS1046ARDB-PB layout which is included into the Design Files package available for download from:

QorIQ® LS1046A Development Board | NXP 

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NXP TechSupport
NXP TechSupport

It is possible to refer to the LS1046ARDB-PB layout which is included into the Design Files package available for download from:

QorIQ® LS1046A Development Board | NXP 

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Contributor II

Yes, thank you. That is essentially what I needed.

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