Accessing LS1021A to PCIe MMIO registers

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Accessing LS1021A to PCIe MMIO registers

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halilgoektepe
Contributor II

I am working with with Towerbaord (LS1021A) and try to access to MMIO registers on a mini-PCIe card (32 bit device) . With existing device tree I get a bus error during accessing to MMIO registers (using UIO framework mmaped to user space). Howto configure device tree to access to a 32 bit PCIe device?

Thank you.

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yipingwang
NXP TechSupport
NXP TechSupport

Hello Halil Goektepe,

Did you use PCI VFIO method to access the EP device?

Would you please provide more detailed description about your test steps?


Have a great day,
Yiping

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halilgoektepe
Contributor II

Hello,

I did not use VFIO. VFIO requires more hardware support by using SMMU.

I use UIO framework.

mini-PCIe device card is a serial I/O device with digital I/O Pins based

on XR17V354 from Exar.

Following steps I performed:

1. Extending uio_pci_generic by supporting BAR0 register.

2. A CLI to read/write to register and memory and to CPU register.

3. I used standard device tree from Freescale.

4. Accesing to config space by using my CLI works.

5. Mmaping MMIO register to user space.

6. Accessing to MMIO register of the EP: Bus error.

I think address translation does not work correctly.

Best regards.

Halil

Am 14.10.2015 um 13:02 schrieb yipingwang:

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Freescale Community

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Accessing LS1021A to PCIe MMIO registers

reply from Yiping Wang

<http://jiveon.jivesoftware.com/mpss/c/mgA/PDcDAA/t.1r9/R0CkB_lfT--VD8s7AY8u9Q/h1/eqhG5v9o4WV1pCmWaB03cUjBPgRj-2F3GoJUaXSZ409bTuunTxDnqsgk6MvTmPNW-2BIbsMPeMV32yFxUPb-2BtQiSPGCG8wrrcaln-2FLLwVRV4WnU-3D>

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