4GB BAR on PCIe RC on LS1046A

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4GB BAR on PCIe RC on LS1046A

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mdecandia
Contributor III

Hi,

we want to enable a 4GB BAR on each RC on LS1046A.

Making this changes to ls1046a.dtsi

- ranges = <0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0xc0000000>;
+ ranges = <0x82000000 0x0 0x40000000 0x50 0x40000000 0x1 0x00000000>;

makes BARs not accessible.

Is this configuration supported? Are there any limit about it?

Thanks,

Michele

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r8070z
NXP Employee
NXP Employee

When you create an Outbound window, let's say:
To define outbound region as a 64 kB I/O region from 0x8000_0000_D000_0000 to 0x8000_0000_D000_FFFF. The following register settings are required:
1) Write 0xd0000000 to Address {0x700 +0x20C} to set the Lower Base Address.
2) Write 0x80000000 to Address {0x700 +0x210} to set the Upper Base Address.
3) Write 0xd000ffff to Address {0x700 +0x214} to set the Limit Address.

Limit register --> It is the end address of the address region to be translated.

Your code is not able to create a 4GB region because the start address is 0x50_40000000, and the limit register is only a 32-bit register. At max, the region will define as 0x50_40000000 to 0x50_FFFFFFFF (~3GB).

In order to create a 4GB, the following changes should work:
- ranges = <0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0xc0000000>;
+ ranges = <0x82000000 0x1 0x00000000 0x50 0x00000000 0x1 0x00000000>;

Base addr --> Translation addr
0x50_0000_0000 --> 0x1_0000_0000
0x50_FFFF_FFFF --> 0x1_FFFF_FFFF

Note: You need to align the window address with its size.

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