The integrated flash controller (IFC) is used to interface with external asynchronous/synchronous NAND flash, asynchronous NOR flash, SRAM, generic ASIC memory and EPROM. This document introduces how to configure IFC controller on QorIQ LS, T and P series custom boards, uses LS1043 custom board integrating NAND Flash MT29F64G08CBCBBH1 as an example to demonstrate IFC flash timing parameters calculation and control registers configuration, CodeWarrior initialization file customization and u-boot source code porting. 1. IFC Memory Mapped Registers Introduction 2. Calculate IFC Flash Timing Values and Configure Control Registers 3. Customize CodeWarrior Initialization File with the Calculated IFC Timing 4. Porting U-BOOT Source with the Calculated IFC Timing

The u-boot in SDK2.0 has a bug on SGMII2.5 support. Need to add the patch.

This document introduces how to configure RCW to support GPIO on LS1043 platform, how to configure Linux Kernel to load Linux GPIO driver to access GPIO from SYSFS and using loopback method to do verification on the target board. RCW configuration to support GPIO Configure GPIO driver in Linux Kernel Verify GPIO on the target board

This file shows up LS1024A GMAC2 debug, no software support in barebox only workable in kernel. and If using RTL Phy need to add TX_CLK and RX_CLK delay.

The attached patch is to support Aquantia AQR107 in LS1043A.

The attached patch is to support DDR3L in LS1043A. The SDK version is Linux-LS1043A-SDK-V0.5-SOURCE-20151223-yocto.iso. Not SDK2.0. The DDR3L part number is two Winbond W632GU6KB(16M x 8 banks x 16 bits DDR3L SDRAM).

Currently rate limiting is supported on TX side only via IOCTL call FM_PORT_IOC_SET_RATE_LIMIT. A user-space application has to be implement which opens the character driver interface of the TX port and issue the IOCTL. The rate_limit structure (mentioned below) has to be filled to implement the restriction.   For example:   fd = open ("/dev/fm0_port_tx5", O_RDWR);   err = ioctl(fd, FM_PORT_IOC_SET_RATE_LIMIT, &fm_port);   Structure to pass to the IOCTL: /**************************************************************************//** @Description@@   A structure for defining Tx rate limiting (Must match struct t_FmPortRateLimit defined in fm_port_ext.h) *//***************************************************************************/ typedef struct ioc_fm_port_rate_limit_t { uint16_t max_burst_size;         /**< in KBytes for Tx ports, in frames for offline parsing ports. (note that for early chips burst size is rounded up to a multiply of 1000 frames).*/     uint32_t rate_limit; /**< in Kb/sec for Tx ports, in frame/sec for offline parsing ports. Rate limit refers to data rate (rather than line rate). */ ioc_fm_port_dual_rate_limiter_scale_down rate_limit_divider; /**< For offline parsing ports only. Not-valid for some earlier chip revisions */ } ioc_fm_port_rate_limit_t; Further information in the below link. http://www.freescale.com/infocenter/index.jsp?topic=%2FQORIQSDK%2F2283674.html