Issue description.
The CodeWarrior® TAP enables target system debugging via a standard debug port (usually JTAG) while connected to a developer's workstation via Ethernet or USB.
This the hardware debug tool(JTAG debug tool) to debug the DN MPU.
You could find the tool from below link
https://www.nxp.com/design/design-center/development-boards-and-designs/CW_TAP
To debug the Layerscape MPU, should select
CWH-CTP-BASE-HE and CWH-CTP-CTX10-YE
In fact, the CWH-CTP-CTX10-YE will adapt the different signal definition, one connector will be insert to the CWH-CTP-BASE-HE, and another one(totally 10 pins) will be used to debug the Layerscape MPU.
You could find the definition of the JTAG connector(CWH-CTP-CTX10-YE, 10pins) on the Layerscape board. Pin 10 (SRST)is the signal of this documents to should add workaround.
In the CodeWarrior TAP Probe User Guide, the SRST(SRST_B) is Open-drain. So the voltage of this signal should be decided by the pull-up voltage connect to it.
See the schematics part below, pin 10 (JTAG_RST_B) should be 1.8V, but in fact it’s not.
The test signal will be exceed 1.8V to about 2.6V.
If you connect this pin directly to the Layerscape MPU, it will violate the SPEC of the VIN.
Workaround.
Workaround for the user would be to use an external circuit (level shifter/limiter) for the affected signal(s).
- level-shifter/limiter
CWTAP <=> probe tip <=> (level-shifter/limiter) <=> target
Please refer to FRWYLS1046A-PA, use the AND gate 74AUP1G11GW similar components which the Overvoltage tolerant inputs to 3.6 V.
- Logic Device
Customer could also refer to LS1046ARDB CPLD LCMXO1200C-3FTN256C
and LX2160ARDB CPLD EPM2210F256C5N, even the CPLD IO Voltage is 1.8V, no issue with 2.6V input on 1.8V IO ports.
