Still bug in AN11538 SCTimer/PWM cookbook

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Still bug in AN11538 SCTimer/PWM cookbook

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NXP Employee
NXP Employee
Content originally posted in LPCWare by 1234567890 on Tue Jun 02 05:17:32 MST 2015
Fig 2 on page 6 of AN11538 Rev. 3.1:

LPC_SCT->MATCHREL[0].U = SystemCoreClock/100; 
// match 0 @ 100 Hz = 10 msec


must be

LPC_SCT->MATCHREL[0].U = (SystemCoreClock/100)-1; 
// match 0 @ 100 Hz = 10 msec

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Contributor I

why?  

Set the corresponding event bit in the LIMIT register for the event to set an upper
limit for the counter.
When a limit event occurs in unidirectional mode, the counter is cleared to zero
and begins counting up on the next clock edge.
When a limit event occurs in bidirectional mode, the counter begins to count down
from the current value on the next clock edge. 

if SystemCoreClock = 10MHz,when it is 10000000,clear to zero,next clock edge it is 1,so it realy is 1 to 9999999? 

 
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