RIT - What is it useful for?

lpcware · ‎06-15-2016

Content originally posted in LPCWare by larryvc on Wed May 18 15:43:04 MST 2011
I have just read Chapter 22 of UM10360 and understand how to use the RIT and the differences between it and the System Tick Timer.

I have a question about paragraph 22.2.

22.2 Description
The Repetitive Interrupt Timer provides a versatile means of generating interrupts at
specified time intervals, without using a standard timer. It is intended for repeating
interrupts that aren’t related to Operating System interrupts. However, it could be used as
an alternative to the Cortex-M3 System Tick Timer (Section 23.1) if there are different
system requirements.

The last sentence in the paragraph is very vague.

My question is what could it be useful for either as an alternative to the systick timer or stand alone? Examples or ideas would be helpful.

Thanks,
Larry

lpcware · ‎06-15-2016

Content originally posted in LPCWare by larryvc on Sat May 21 10:17:20 MST 2011
Back to RIT.

Reference posts 3 and 5 and the theoretical ideas there.

I know we can read RICOUNTER to determine which count triggered the interrupt.

What would be the best way to implement pulsing two or more GPIO pins based on the interrupt and the value of RICOUNTER.

Most likely not in the ISR itself, but if the interrupts happen too quickly external routines would probably be preempted by another interrupt anyways.

I suppose there are other ways to accomplish this on the LPC1769, with timers, and any suggestions are ok.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by larryvc on Fri May 20 12:12:51 MST 2011

Quote: igorsk
The conventional meaning of "mask" (e.g. "to mask an interrupt") is "to disable/suppress". So, putting 1 means to disable updating of that pin.

I agree with ArneB. I think mask can be used for enable or disable depending on what the mask does. It just seems more natural to to use "1s" for determining what is enabled/disabled. Did that make sense?:confused::)

If the mask is used to disable features use a "1" to accomplish that.

If the mask is used to enable features use a "1" to accomplish that.

If you want to set a mask for which pins on an LPC1769 GPIO port are changeable use "1s" not "0s". Don't do this it won't work, this is only an example.;)

lpcware · ‎06-15-2016

Content originally posted in LPCWare by ArneB on Fri May 20 06:33:20 MST 2011
Hmmm, i disagree.
If I read "mask" in a user manual I am always thinking of an "AND" operation. Therefore a "1" in the mask register would mark a changeable bit and a "0" a non-changeable in my mind.
Hope, that NXP could fix that in future devices. Or even make the behavior the same for all Cortex LPC families...

lpcware · ‎06-15-2016

Content originally posted in LPCWare by igorsk on Fri May 20 04:25:25 MST 2011

Quote: larryvc
I knew about the differences in masking and accessing. I just was wondering why they used zeros to unmask on the 17xx, they could have used ones to maintain some consistency. eg. put a one here to allow a change to occur.

The conventional meaning of "mask" (e.g. "to mask an interrupt") is "to disable/suppress". So, putting 1 means to disable updating of that pin.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by larryvc on Thu May 19 17:34:27 MST 2011

Quote: jharwood
The masking for GPIOs is quite different for 17xx vs the others. For 17xx it is a 32 bit mask register with zeroes meaning 'unmask'. The others use a type of 'bit-banding' where GPIOnDATA register addresses 0x0000 to 0x3ff8 map to the various combinations of bits that are masked or not.

I knew about the differences in masking and accessing. I just was wondering why they used zeros to unmask on the 17xx, they could have used ones to maintain some consistency. eg. put a one here to allow a change to occur. It must have been easier to implement the GPIO block that way or maybe this goes back to the 2xxx series that the 17xxs replaced.

I'll have to be careful when I start using the 11xxs and [B]12xxs [/B]to make sure I don't get the masking inverted.

Quote: jharwood
Or, are you referring to GPIO interrupt masking?

No. I haven't had time to look at that yet.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by jharwood on Thu May 19 16:56:07 MST 2011

Quote: larryvc
On a little bit of a tangent, I noticed that the masks for 17xx GPIOs are opposite of the 13xx,12xx,11xx GPIOs. ie. zeros on the 1769, ones on the others. At least that is what I'm getting from the UMs. Am I correct on that?

The masking for GPIOs is quite different for 17xx vs the others. For 17xx it is a 32 bit mask register with zeroes meaning 'unmask'. The others use a type of 'bit-banding' where GPIOnDATA register addresses 0x0000 to 0x3ff8 map to the various combinations of bits that are masked or not.

Or, are you referring to GPIO interrupt masking?

lpcware · ‎06-15-2016

Content originally posted in LPCWare by larryvc on Wed May 18 20:31:57 MST 2011

Quote: jharwood
Precise timing of Vsync and Hsync for VGA display signals?

Naw. Use a propeller chip for that.;)

Actually a couple of RITs would be great to have. I'm going to start writing some routines to test it. I need to spend some money on a new scope too so I can look at timing relationships. I could time it in software but it will be easier to trigger on a couple of ouputs. I like the PicoScopes but may look at other alternatives.

Quote: jharwood
Mask: 1101
Cmp: 1001
Ctr:    10x1 <-- fires int where x = don't care

Int:   1001 d9
Int:   1011 d11

OK. That confirms what I figured out on paper while having dinner. Napkins are great.:rolleyes:

On a little bit of a tangent, I noticed that the masks for 17xx GPIOs are opposite of the 13xx,12xx,11xx GPIOs. ie. zeros on the 1769, ones on the others. At least that is what I'm getting from the UMs. Am I correct on that?

lpcware · ‎06-15-2016

Content originally posted in LPCWare by jharwood on Wed May 18 19:52:38 MST 2011

Quote: larryvc
Yea that's what I came to the conclusion about. That is a nice feature. Right now I can't conceptualize anything to use it for.

Long and short timeouts for inter-networking, particularly with UDP protocols?

Precise timing of Vsync and Hsync for VGA display signals?

Quote:
Wouldn't it also fire on 13 and 15 decimal or am I not understanding the masking correctly.

Mask: 1101
Cmp: 1001
Ctr:    10x1 <-- fires int where x = don't care

Int:   1001 d9
Int:   1011 d11

lpcware · ‎06-15-2016

Content originally posted in LPCWare by larryvc on Wed May 18 18:42:15 MST 2011

Quote: jharwood
My take on it is that it can generate interrupts on multiple divisions of PCLK.

Then an interrupt would fire when the count reached 9 and 11 decimal.
This would result in interrupts on PCLK/10 and PCLK/12

:confused: I thinks that's right :confused:

Yea that's what I came to the conclusion about. That is a nice feature. Right now I can't conceptualize anything to use it for.

Wouldn't it also fire on 13 and 15 decimal or am I not understanding the masking correctly.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by jharwood on Wed May 18 17:44:27 MST 2011
My take on it is that it can generate interrupts on multiple divisions of PCLK.

Take an artificially simplified example:

If the mask is set to (binary) 1101 and
compare is set to 1001 and
all the upper (left most) bits of the mask are all 0's and
the counter is free running (doesn't reset to zero on interrupt)

Then an interrupt would fire when the count reached 9 and 11 decimal.
This would result in interrupts on PCLK/10 and PCLK/12

:confused: I thinks that's right :confused:

lpcware · ‎06-15-2016

Content originally posted in LPCWare by larryvc on Wed May 18 16:36:08 MST 2011
What I'm trying to understand is this.

With all the other timer options available on the LPC1769 does the RIT really have anything special to offer that the others don't?

Why would we use the RIT in lieu of the others?