Odd dissasembly lisitng in debugger

lpcware · ‎06-15-2016

Content originally posted in LPCWare by mrob on Tue Aug 21 12:42:58 MST 2012
Hi,

I am working on a project with an LPC11U24/401, and I'm having an interesting issue. When I was attempting to debug my device, it wasn't performing as expected, so I took a look at the disassembly listing and noticed that the asm for a call didn't look right. When I compare it to the list file, it is vastly different.

------------------------------
- Dissasembly when debugging -
------------------------------
                            main:
00000638: main+0              movs r2, #0
234                           SetupLeds_Test();
0000063a: main+2              str r2, [r3, #32]
0000063c: main+4              b.n 0x644 <main+12>
236                           SystemCoreClockUpdate();
0000063e: main+6              nop ; (mov r8, r8)
00000640: main+8              ldr r2, [sp, #4]
238                           LPC_GPIO->DIR[0] &= ~(0x1<<1);
00000642: main+10             adds r2, #1
00000644: main+12             str r2, [sp, #4]
00000646: main+14             ldr r2, [sp, #4]
00000648: main+16             cmp r2, #199    ; 0xc7
0000064a: main+18             bls.n 0x63e <main+6>
0000064c: main+20             movs r2, #1
0000064e: main+22             movs r1, #0
00000650: main+24             str r2, [r3, #64]       ; 0x40

-------------
- List File -
-------------
int main (void) 
{
     638:    b510          push    {r4, lr}

  /* It's very important that POWERDOWN_MODE_USB_WAKEUP and REMOTE_WAKEUP_ENABLE
  flags should not be turned on at the same time!!!!!! */
    

  SetupLeds_Test();
     63a:    f7ff ffe5     bl    608 <SetupLeds_Test>

  SystemCoreClockUpdate();
     63e:    f001 f8b5     bl    17ac <SystemCoreClockUpdate>

  LPC_GPIO->DIR[0] &= ~(0x1<<1);
     642:    22a0          movs    r2, #160    ; 0xa0
     644:    2380          movs    r3, #128    ; 0x80
     646:    019b          lsls    r3, r3, #6
     648:    05d2          lsls    r2, r2, #23
     64a:    58d1          ldr    r1, [r2, r3]
     64c:    2002          movs    r0, #2
     64e:    4381          bics    r1, r0
     650:    50d1          str    r1, [r2, r3]

I checked it out on a second board, and it seems to work fine on that one.

So, the question is: Did i burn out the processor somehow, or did I somehow put it into a strange operating mode with a different instruction set?
I only bring up the second as a though, since I noticed the disassembly had "b.n." and "bls.n" instructions that i didn't see in the LPC11Uxx user manual.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by TheFallGuy on Tue Aug 21 14:44:48 MST 2012
This is obviously completely different code. So you are not debugging what you think you are debugging.

Check the debug log to see if your application actually got programmed.

If it works on a 2nd board, maybe there is a problem with the 1st..,