Content originally posted in LPCWare by cfb on Fri Sep 14 07:34:15 MST 2012
My guess was wrong :o However, according to the ARMv7-M Architecture Reference Manual there are three different possible encodings (called T1, T2 and T3) for the ADD (register) instruction. My interpretation is that T2 is used if the <Rd> is omitted but a shift is only allowed in T3.
Just to complicate things even further, there is another note:
"Inside an IT block, if ADD<c> <Rd>,<Rn>,<Rd> cannot be assembled using encoding T1, it is assembled using encoding T2 as though ADD<c> <Rd>,<Rn> had been written. To prevent this happening, use the .W qualifier."
See Page A7-224 for more detail.