Content originally posted in LPCWare by RA1981 on Wed Jul 20 14:43:19 MST 2011
Hi,
unfortunately it seems that the search function couldn't find 'I2C'. I assume that at least four characters must be entered, so I'm sorry if this question has been already asked.
I want to dig deeper into I2C. So I build a small test circuit for LPCxpresso boards. Now, the software needs to be written :)
I know about the examples, but they're just that - examples. Written for special purposes like EEPROM or something like that.
But I couldn't find a generic approach which allows to have the I2C routines and just build the device driver on top of them, without having to modify the I2C routines and interrupt.
So, I thought about possible implementations for a generic driver. Reading the LPC 11xx/13xx/17xx user manual shows up that for most of the I2C status codes there are two or more possible status codes following, depending on the situation and the need of the device driver.
Now, I wonder if the following approach would be suitable:
A buffer is used for communication, along with transmit and receive counters and pointers. If the transmit counter is non-zero, the buffer will be sent (LPC acting as a master transmitter). The same with the receive counter, but LPC as a master receiver. If both are non-zero, the data will be sent and a repeated start instead of a stop is generated and the data is read.
So, that's the easy part and this approach is mostly used as far as I can see.
Now, assume there are (at least) two devices on the bus. For one device it is neccessary to repeat a transfer if e.g. the device sends a unexpected NACK during the transfer. For the other device it isn't neccessary or even not allowed to repeat the transfer (e.g. because the other device must be served within a given time or something like that).
One approach would be to write the interrupt service routine in a way that distinguishes between the two devices and acting accordingly. But that wouldn't be generic.
So, what about two additional status bytes for each data byte in the buffer? Each status byte contains the next status depending on a ACK/NACK. This allows to write a generic I2C driver, where the buffer contents also controls the behaviour of the communication.
Of course, at the moment this approach is only seen from master side, slave implementation is still open.
I hope it's clear what I mean :) What do you think of this approach? To complicated? Worth a try?
Regards,
Ralf