Diff b/w true open drain & open drain pin

[lpcware]

Content originally posted in LPCWare by Deepak Bansal on Thu Oct 04 04:42:27 MST 2012
What is the diff b/w true open drain & open drain pin.

WRT LPC1317, P0.4 & P0.5 are true open drain while other are not

[lpcware]

Content originally posted in LPCWare by tha on Tue Oct 09 14:49:54 MST 2012
You are correct.  For the true open drain pins, the voltage seen on it can go above VDD.  But there is a limitation.  Since these pins are design to be I2C compliant, it would support up to 5.5V max.

[lpcware]

Content originally posted in LPCWare by Deepak Bansal on Mon Oct 08 23:52:44 MST 2012
Hi I have read in user manual that for normal pins

[B]This is not a true open-drain
mode. Input cannot be pulled up above VDD.[/B].

Does that mean that true open drain can be pulled above VCC also keeping its specified sink current in limit. If yes, then upto which voltage level this can be done

[lpcware]

Content originally posted in LPCWare by tha on Thu Oct 04 17:21:30 MST 2012
For the true open drain, it is what it say.  The output stage is basically a FET with the drain exposed.  For the standard IO, this is not true.  The pad is not tied directly to the drain, but rather some circuitry which mimics an open drain characteristic, refer to Fig 8 of the UM.