ADC sample and hold

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ADC sample and hold

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by mhjerde on Fri Jun 04 00:30:01 MST 2010
I need to sample a pulse with a duration between 0.2 uS and 28 uS. According to the UM the conversion time for the LPC1343 is >= 2.44 uS.

Does the signal need to be present and stable for the complete conversion period or is there a sample and hold circuit internal to the LPC1343 that holds the input for the ADC?

Cheers,
Morten
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by elef on Tue Jul 17 23:32:11 MST 2012
Are there any details from NXP regarding the ADC timings, especially the sample and hold?
I've searched the data sheet and user manuals, cant find anything. Anyone got any ideas? Specifically LPC17xx

Thanks.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by peufeu on Tue May 31 14:33:52 MST 2011
> Something like this would be worth an application note

Yeah, experimenting is good but some real specifications are much better. If someone at NXP wrote an appnote that would be nice.

> In no way I have plans to stress the ADC with these kind of signals

It's commonplace : say you got a H-bridge driving a motor by PWM,

http://sketchtag.com/KRFClUA72A

then you want to sample the current in the sense resistor (usually in the bridge ground) when the bridge actually sends the current through the motor and the sense resistor (ie, MOS 1+4 or 2+3 are driven) and not when MOS 3+4 are driven shorting the motor... so it takes some ADC/PWM synchronization.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Rob65 on Tue May 31 04:23:50 MST 2011
Kudos to peufeu !


Quote: peufeu

- trigger the ADC at T-10 core clocks (T-0.2µs)
- sample would be taken at T+5...T+10 clocks (T+0.1 .. 0.2 µs)
- the pulse should not end before T+20 clocks (T+0.4 µs)



Very nice piece of work!
In no way I have plans to stress the ADC with these kind of signals but it is good to know there is a well defined sample and hold.
Something like this would be worth an application note :D

Regards,

Rob
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by peufeu on Tue May 31 02:42:41 MST 2011
OK...

LPC1114, core clock 48 MHz
CT32B0_MAT0 PWM output generates pulse of length 120 clocks = 2.5µs
ADC clock is main clock divided by 11, ie 4.36 MHz
ADC is synchronized to CT32B0_MAT1 which is set to a variable delay.
attached files : plot of adc value versus delay

horizontally, each pixel is 1 core clock cycle.

[B]Test 1 :[/B] PWM output -> RC (1Kohm+450pF) -> ADC

-> there is actually a sample & hold (as expected...)

[B]Test 2 :[/B] PWM output -> 1Kohm -> ADC

[B]Test 3 :[/B]PWM output -> ADC

- slew rate is a bit higher than in test 2 (which is normal since the 1K resistor makes a RC with the input capacitance)

- slew rate of the track&hold input stage is around 30-40V/µs, ie with very low source impedance it takes about 4 core clocks to settle

- aperture jitter is very low (much less than 1 core clock cycle)

Looking at the output logs, with the PWM outputs a rising edge at T=0 :

- if ADC is triggered at T-15 core clocks, it samples 3.3V
- if ADC is triggered at T-20 core clocks, it samples 0V
- if ADC is triggered in between, it samples the edge

So, to be safe (adding 5 clocks safety margin), I'd say that if you want to sample a pulse that starts at T,

- trigger the ADC at T-10 core clocks (T-0.2µs)
- sample would be taken at T+5...T+10 clocks (T+0.1 .. 0.2 µs)
- the pulse should not end before T+20 clocks (T+0.4 µs)

So it is possible to sample a 1 µs pulse (even a 0.5 µs pulse) with this ADC. Nice !
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by peufeu on Mon May 30 11:43:36 MST 2011
"Track and Hold" and "Sample and Hold" actually mean almost the same stuff.

"Track and Hold ADC" is a meaningless phrase. You can have a track and hold amplifier, followed by a SAR ADC (or another type of ADC).

Say you have a track and hold amplifier, when you ask it to track, the output tracks the input (ie, it behaves like a normal amplifier or follower). When you ask it to hold, it holds the value constant, which is exactly the same thing as taking a sample and holding it.  Except a "sample and hold" circuit doesn't imply the output is able to track the input.

But since the ADC is only interested in the "hold" part, it's exactly the same.

Ask the Maxim guys if you dont trust me :

http://www.maxim-ic.com/app-notes/index.mvp/id/641

Which makes this comment pretty obscure :

> Nope we have a track and hold no sample and hold.
> So it means that the signal should be present
> and stable for at least 2,44 us.

An ADC of the Successive Approximation (SAR) variety, without a track and hold in front of it is pretty useless, since if the input signal changes a bit during the conversion time, you get garbage.


Quote:
For a 10-bit conversion in the LPC1100/1300 the ADC signal is sampled in the first clock, and converted in the remaining 10 clocks. After the first clock the external signal has no influence on the conversion result anymore. Therefore the required minimum time of stable signal is 1 clock at 4.5 MHz = 0.22 us. The timing of the ADC start trigger is very important. You could use a timer or an external trigger for example. Be aware that the ADC does not start imediately after you trigger it; it has a delay of two initialisation clocks.



Now this looks a lot better (ie, what you'd expect from an ADC inside such an excellent microcontroller).

Still a bit of ambiguity :

> the ADC signal is sampled in the first clock, and converted in the remaining 10 clocks
> the ADC does not start imediately after you trigger it; it has a delay of two initialisation clocks

So I presume the sequence of events is :

- trigger
- 2 ADC clocks : ADC initialization
- 1 ADC clock : sampling
- 10 ADC clocks : conversion

This would mean :

> the ADC does not start imediately after you trigger it; it has a delay of two initialisation clocks
> the ADC signal is sampled in the first clock [I]after there two initialization clocks[/I], and converted in the remaining 10 clocks

There is still some ambiguity about trigger timing.

Say the chip runs at 48 MHz, and the ADC clock is at 4.36 MHz, or 48 divided by 11. So, an ADC clock cycle corresponds to 11 main clocks.

The ADC clock could be free running. For instance, if the trigger happens in the middle of an ADC clock cycle, it would only be acted upon at the end of this cycle. This would introduce a jitter of 0-10 main clock cycles.

The ADC clock could be synchronized with the trigger. That would be true if the ADC trigger resets the ADC clock prescaler. Then, you could know for sure that the sampling occurs 2 ADC clocks, or 22 main clocks after trigger.

[B]The datasheet should really describe all this in excruciating detail[/B] (atmel does it after all) since sampling your signals with accurate timing is quite important in many cases. Especially when you want to sample the current in a H-Bridge at the precise moment the MOS's send said current through the sense resistor.

I'm going to do a little experiment :

- set one pin as PWM to output a pulse (of variable length)
- send this to the ADC input and synchronize the ADC with it (using variable delay)

This should be interesting.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Rob65 on Mon May 30 00:59:08 MST 2011
Dear NXP,

sorry if I sounded a bit frustrated in my last post.
Could you please check if there is a [I]sample&hold[/I] or [I]track&hold[/I] in the lpc11xx/13xx/17xx or if we need an external circuit to do this?

There just was a second question (link to thread) from a user wondering what to do.

Regards,

Rob
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Rob65 on Tue May 03 08:12:36 MST 2011
I am getting confused by this:

Quote: NXP_Europe
Hi Morten,
Nope we have a track and hold no sample and hold. So it means that the signal should be present and stable for at least 2,44 us.

Kind regards,



OK, clear. No sample&hold, no track and hold.


Quote: NXP_Europe
For a 10-bit conversion in the LPC1100/1300 the ADC signal is [COLOR=Red][B]sampled in the first clock[/B][/COLOR], and converted in the remaining 10 clocks. After the first clock the external signal has no influence on the conversion result anymore. Therefore the required minimum time of stable signal is 1 clock at 4.5 MHz = 0.22 us.  The timing of the ADC start trigger is very important. You could use a timer or an external trigger for example. Be aware that the ADC does not start imediately after you trigger it; it has a delay of two initialisation clocks.



And here you state it does have a sample and hold ???

Neither the datasheet nor the user manual give us any hint as to if a sample&hold is used. But of course having a burst mode ADC makes no sense when there is no S&H ...

Please have a look at this and update the datasheet/user manual to reflect the silicon. And while you're at it, please also tell me where I can find the connections for the I2C_PCLK or PCLK_I2C (both terms are used in the user manual) I still cannot find these in the latest manual.

Rob

P.s: sorry if I sound a bit frustrated, this may be because I am :eek:
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by NXP_Europe on Tue May 03 04:47:10 MST 2011
For a 10-bit conversion in the LPC1100/1300 the ADC signal is sampled in the first clock, and converted in the remaining 10 clocks. After the first clock the external signal has no influence on the conversion result anymore. Therefore the required minimum time of stable signal is 1 clock at 4.5 MHz = 0.22 us.  The timing of the ADC start trigger is very important. You could use a timer or an external trigger for example. Be aware that the ADC does not start imediately after you trigger it; it has a delay of two initialisation clocks.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by sperdomo on Sat Jun 05 02:39:47 MST 2010
Concerning the LPC1114 A/D Control Register (AD0CR), the datasheet says:[FONT=Arial][SIZE=1][FONT=Arial][SIZE=1]
[FONT=Times New Roman][SIZE=3][COLOR=black][/COLOR][/SIZE][/FONT]
[FONT=Times New Roman][SIZE=3][COLOR=black][I][B]7:0 SEL Selects which of the AD7:0 pins is (are) to be [COLOR=red]sampled[/COLOR] and converted.[/B][/I][/COLOR][/SIZE][/FONT]
[/SIZE][/FONT][/SIZE][/FONT][B][FONT=Arial][SIZE=1][FONT=Arial][SIZE=1][FONT=Arial][SIZE=1][/SIZE][/FONT][/SIZE][/FONT][/SIZE][/FONT][/B]
and

[B][I]15:8 CLKDIV    ... [/I][I]. Typically, software should program the smallest[/I][/B]
[LEFT][B][I]value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such [/I][I]as a [COLOR=red]high-impedance analog source) a slower clock may be desirable.[/COLOR][/I][/B]
[B][I][COLOR=#ff0000][/COLOR][/I][/B]
[COLOR=black]These phrases made me think it has S/H but.  [/COLOR]Is this NXP team reply LPC1114 applicable or has it S/H incorporated ?.[/LEFT]
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by NXP_Europe on Fri Jun 04 07:34:10 MST 2010
Hi Morten,
Nope we have a track and hold no sample and hold. So it means that the signal should be present and stable for at least 2,44 us.

Kind regards,
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