Content originally posted in LPCWare by peufeu on Tue May 31 02:42:41 MST 2011
OK...
LPC1114, core clock 48 MHz
CT32B0_MAT0 PWM output generates pulse of length 120 clocks = 2.5µs
ADC clock is main clock divided by 11, ie 4.36 MHz
ADC is synchronized to CT32B0_MAT1 which is set to a variable delay.
attached files : plot of adc value versus delay
horizontally, each pixel is 1 core clock cycle.
[B]Test 1 :[/B] PWM output -> RC (1Kohm+450pF) -> ADC
-> there is actually a sample & hold (as expected...)
[B]Test 2 :[/B] PWM output -> 1Kohm -> ADC
[B]Test 3 :[/B]PWM output -> ADC
- slew rate is a bit higher than in test 2 (which is normal since the 1K resistor makes a RC with the input capacitance)
- slew rate of the track&hold input stage is around 30-40V/µs, ie with very low source impedance it takes about 4 core clocks to settle
- aperture jitter is very low (much less than 1 core clock cycle)
Looking at the output logs, with the PWM outputs a rising edge at T=0 :
- if ADC is triggered at T-15 core clocks, it samples 3.3V
- if ADC is triggered at T-20 core clocks, it samples 0V
- if ADC is triggered in between, it samples the edge
So, to be safe (adding 5 clocks safety margin), I'd say that if you want to sample a pulse that starts at T,
- trigger the ADC at T-10 core clocks (T-0.2µs)
- sample would be taken at T+5...T+10 clocks (T+0.1 .. 0.2 µs)
- the pulse should not end before T+20 clocks (T+0.4 µs)
So it is possible to sample a 1 µs pulse (even a 0.5 µs pulse) with this ADC. Nice !