refresh period in EMC block

[lpcware]

Content originally posted in LPCWare by hamedb3269 on Sun Feb 22 08:01:53 MST 2015
How to calculate the DYNAMICREFRESH register in EMC block?
I am using LPC1788 microcontroller.
I am using K4S561632C SDRAM.
EMCCLK --> 120MHZ
64ms refresh period (8k cycle)

[lpcware]

Content originally posted in LPCWare by Prabhakaran_Raja on Thu Feb 18 07:11:01 MST 2016
Thanks,
I have LPC4357 xplorer++ evl board and NXP LPC-Link debugger.
i using LPCXpresso v7.9.2 IDE.
In my evl board we have MT48LC8M32B2B5-6 SDRAM.
but i'm trying to interface SDRAM in all the way but i'm not able to interface with SDRAM.
some keil examples are there but i cannot flash the *.afx through  LPC-Link .


Please any one suggest how flash using LPC-Link with keil examples?
AND please suggest any direct example of SDRAM interface using  LPCXpresso v7.9.2 IDE.

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Wed Feb 17 07:57:35 MST 2016

---

Quote: Prabhakaran_Raja
Hi,

I need some more understand in this.
what is clock speed in "Calculate the clock speed". is it main clk or emc clk?
and Please help this one also,

I am using LPC4357 microcontroller.
I am using MT48LC8M32B2 SDRAM.
EMCCLK --> 102MHz
Core clk --> 204MHz
64ms, 4,096-cycle refresh (15.6μs/row)

Please what could be the DYNAMICREFRESH Value?

---

Please double check the data sheet (not user manual) for your device as you may be over clocking the memory bus! as in my previous post.
(I do not use 43xx series.)
It is EMC clock (on 1778, this is either the same as or one half of the CPU clock depending on a setting in the system block, but I understand
that clock divisors are much more complicated in the 43xx).

Regards, Mike.

[lpcware]

Content originally posted in LPCWare by Prabhakaran_Raja on Wed Feb 17 02:34:43 MST 2016
Hi,

I need some more understand in this.
what is clock speed in "Calculate the clock speed". is it main clk or emc clk?
and Please help this one also,

I am using LPC4357 microcontroller.
I am using MT48LC8M32B2 SDRAM.
EMCCLK --> 102MHz
Core clk --> 204MHz
64ms, 4,096-cycle refresh (15.6μs/row)

Please what could be the DYNAMICREFRESH Value?

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Sun Feb 22 08:50:19 MST 2015
Firstly, your EMC clock excees the specification by 150%. The max is 80MHz, see your datasheet!
This won't be either stable or supported.

1) Calculate the refresh interval: 64ms/8192 = 7.8125 usec
2) Calculate the clock speed: 1/120Mhz = 8.333 nsec
3) Calculate nbr clocks (round up!) = 7.8125 * 1000 / 8.333 [NB * 1000 to convert usec to nsec]
  = 937.5; round up to 938

4) Divide by 16 [Register is in multiples of 16 clocks] = 58.625 = 58 [Round down!]

All you needed was (a) to read the UM and (b) basic arithmetic!

Mike