Hi，
I download the errata of LPC43x0 from the link:
https://www.nxp.com/docs/en/errata/ES_LPC43X0.pdf
There are two parts for the EMC module in the errata:
This is the EMC description:
3.3 EMC.1
Introduction:
The LPC43x0 parts contain an External Memory Controller (EMC) capable of interfacing
to external SDRAM, SRAM, and asynchronous parallel flash memories. The EMC can be
configured to operate at the processor core frequency (BASE_M4_CLOCK) or the core
frequency divided by 2.
Problem:
When operated in the divide by 2 mode (EMC_CLK_SEL, bit 16 CREG6, Address
0x4004.312C), the duty cycle of the clock is not the typical 50 % which shortens the setup
time. This could impact designs with an EMC running faster than 100 MHz in divide by 2
mode (which corresponds to a maximum core frequency of 200 MHz).
Work-around:
If the external bus is running greater than 100 MHz in divide by 2 clock mode, consider the
following:
1. When using only one external chip, use the CLK1 or CLK3 pin to drive the SDRAM
clock for best performance. CLK0 and CLK2 pins are us
3.4 EMC.2
Introduction:
The LPC43xx parts contain an External Memory Controller (EMC) capable of interfacing
to external SDRAM, SRAM, and asynchronous parallel flash memories. The EMC can be
configured to operate at the processor core frequency (BASE_M4_CLOCK) or the core
frequency divided by 2.
Problem:
For SDRAM, the electrical characteristic of the LQFP144 and LQFP208 packages limits
the operating frequency of the EMC to a certain level, which is lower than the specified
value in the data sheet. Choosing an SDRAM clock of 72MHz as the upper limit provides
some safety margin. This frequency is either achieved by a core and EMC frequency of
72MHz, or by a 144MHz core and a 72MHz EMC frequency. However, SDRAM
performance can vary depending on board design and layout.
Work-around:
There is no work-around.
The upper limit of the SDRAM clock frequency is highly dependent on the PCB layout and
the quality of the power supply and de-coupling circuitry.
For the second part in EMC.2, if you use LQFP144 or LQFP208 packages , the SDRAM clock should be less than 72MHz. For the other package, I have checked the data sheet, the minimum EMC clock cycle time is 8.4nS, the maximum EMC clock frequency is 120MHz.
For the first part in EMC.1, it says that you have to use CLK1 or CLK3 for one SDRAM chip case, you use CLK1 for the SDRAM with D0:D15 chip, use CLK3 for SDRAM with D16:D32 chip for two SDRAM case.
I think it is okay when you use 100mHz clock for SDRAM for long time.
Hope it can help you
BR
Xiangjun rong
