issue with lpc4330-m0/m4 NVICs

[lpcware]

Content originally posted in LPCWare by davidjun on Thu Jun 04 07:02:10 MST 2015
Hi,

Chapter 8 (NVIC) in the user manual states that each core supports its own NVIC. I'm not sure what the exact implications are, but is it possible for an interrupt handled by the M0 core to cause delays in processing an M4-based interrupt? There is no shared memory being accessed in either interrupts and no IPC going on.

My setup is as follows:
- SCT is set up to trigger an interrupt based on a CTIN rising edge event. SCT and pin configuration happens on the M4, but the interrupt is enabled and handled on the M0.
- A GPIO pin interrupt is setup, enabled, and handled on the M4.

The SCT handler was moved to the M0 because both interrupts are time critical and events were being missed. Unfortunately, if I do anything but clear the event flag in the M0's SCT handler (e.g., toggle an LED), I lose GPIO pin interrupt events on the M4. This has me stumped since I was under the assumption that the operations on the two cores were more or less independent.

Any ideas or clarification about the NVICs on the dual core would be appreciated.

[lpcware]

Content originally posted in LPCWare by davidjun on Mon Jun 08 14:40:18 MST 2015
Thanks, that solved it. I had set up a scatter file to place the SCT interrupt handler in RAM, but forgot to set up the linker to use it - hence, the M0 code was being run out of SPIFI, which is where the M4 code was being executed from.

[lpcware]

Content originally posted in LPCWare by starblue on Sat Jun 06 11:46:54 MST 2015

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Quote: davidjun
t is it possible for an interrupt handled by the M0 core to cause delays in processing an M4-based interrupt? There is no shared memory being accessed in either interrupts and no IPC going on.

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Normally that should be OK. Are you sure there are no shared memories, in particular flash memory for code?  Can you describe your memory setup?