Hi ChungYu Siang,
To use SDRAM, regardless of the EMC data width, you must have all four byte lane feedback clocks configured in the
System Control Unit (SCU). You may use all four CLKx pins, one for each EMC_CLKx signal, by setting SFSCLKx mode to function 0
Alternatively, SFSCLK0 may be configured for combined EMC_CLK01 (function 5), and SFSCLK2 may be configured
for combined EMC_CLK23 (function 5), When CLK0 and CLK2 pins are configured for function 5, CLK1 and CLK3 pins may be used to drive the SDRAM clock pin, or used for a function other than the EMC_CLK.
Have a great day,
Ping
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